/* * T1040D4RDB/T1042D4RDB Device Tree Source * * Copyright 2015 Freescale Semiconductor Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * Neither the name of Freescale Semiconductor nor the * names of its contributors may be used to endorse or promote products * derived from this software without specific prior written permission. * * * ALTERNATIVELY, this software may be distributed under the terms of the * GNU General Public License ("GPL") as published by the Free Software * Foundation, either version 2 of that License or (at your option) any * later version. * * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ / { reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; bman_fbpr: bman-fbpr { size = <0 0x1000000>; alignment = <0 0x1000000>; }; qman_fqd: qman-fqd { size = <0 0x400000>; alignment = <0 0x400000>; }; qman_pfdr: qman-pfdr { size = <0 0x2000000>; alignment = <0 0x2000000>; }; }; ifc: localbus@ffe124000 { reg = <0xf 0xfe124000 0 0x2000>; ranges = <0 0 0xf 0xe8000000 0x08000000 2 0 0xf 0xff800000 0x00010000 3 0 0xf 0xffdf0000 0x00008000>; nor@0,0 { #address-cells = <1>; #size-cells = <1>; compatible = "cfi-flash"; reg = <0x0 0x0 0x8000000>; bank-width = <2>; device-width = <1>; }; nand@2,0 { #address-cells = <1>; #size-cells = <1>; compatible = "fsl,ifc-nand"; reg = <0x2 0x0 0x10000>; }; cpld@3,0 { compatible = "fsl,t1040d4rdb-cpld"; reg = <3 0 0x300>; }; }; memory { device_type = "memory"; }; dcsr: dcsr@f00000000 { ranges = <0x00000000 0xf 0x00000000 0x01072000>; }; bportals: bman-portals@ff4000000 { ranges = <0x0 0xf 0xf4000000 0x2000000>; }; qportals: qman-portals@ff6000000 { ranges = <0x0 0xf 0xf6000000 0x2000000>; }; soc: soc@ffe000000 { ranges = <0x00000000 0xf 0xfe000000 0x1000000>; reg = <0xf 0xfe000000 0 0x00001000>; spi@110000 { flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "micron,n25q512ax3", "jedec,spi-nor"; reg = <0>; /* input clock */ spi-max-frequency = <10000000>; }; slic@1 { compatible = "maxim,ds26522"; reg = <1>; spi-max-frequency = <2000000>; /* input clock */ }; slic@2 { compatible = "maxim,ds26522"; reg = <2>; spi-max-frequency = <2000000>; /* input clock */ }; }; i2c@118000 { hwmon@4c { compatible = "adi,adt7461"; reg = <0x4c>; }; rtc@68 { compatible = "dallas,ds1337"; reg = <0x68>; interrupts = <0x2 0x1 0 0>; }; }; i2c@118100 { mux@77 { /* * Child nodes of mux depend on which i2c * devices are connected via the mini PCI * connector slot1, the mini PCI connector * slot2, the HDMI connector, and the PEX * slot. Systems with such devices attached * should provide a wrapper .dts file that * includes this one, and adds those nodes */ compatible = "nxp,pca9546"; reg = <0x77>; #address-cells = <1>; #size-cells = <0>; }; }; }; pci0: pcie@ffe240000 { reg = <0xf 0xfe240000 0 0x10000>; ranges = <0x02000000 0 0xe0000000 0xc 0x0 0x0 0x10000000 0x01000000 0 0x0 0xf 0xf8000000 0x0 0x00010000>; pcie@0 { ranges = <0x02000000 0 0xe0000000 0x02000000 0 0xe0000000 0 0x10000000 0x01000000 0 0x00000000 0x01000000 0 0x00000000 0 0x00010000>; }; }; pci1: pcie@ffe250000 { reg = <0xf 0xfe250000 0 0x10000>; ranges = <0x02000000 0 0xe0000000 0xc 0x10000000 0 0x10000000 0x01000000 0 0 0xf 0xf8010000 0 0x00010000>; pcie@0 { ranges = <0x02000000 0 0xe0000000 0x02000000 0 0xe0000000 0 0x10000000 0x01000000 0 0x00000000 0x01000000 0 0x00000000 0 0x00010000>; }; }; pci2: pcie@ffe260000 { reg = <0xf 0xfe260000 0 0x10000>; ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x10000000 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; pcie@0 { ranges = <0x02000000 0 0xe0000000 0x02000000 0 0xe0000000 0 0x10000000 0x01000000 0 0x00000000 0x01000000 0 0x00000000 0 0x00010000>; }; }; pci3: pcie@ffe270000 { reg = <0xf 0xfe270000 0 0x10000>; ranges = <0x02000000 0 0xe0000000 0xc 0x30000000 0 0x10000000 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>; pcie@0 { ranges = <0x02000000 0 0xe0000000 0x02000000 0 0xe0000000 0 0x10000000 0x01000000 0 0x00000000 0x01000000 0 0x00000000 0 0x00010000>; }; }; qe: qe@ffe140000 { ranges = <0x0 0xf 0xfe140000 0x40000>; reg = <0xf 0xfe140000 0 0x480>; brg-frequency = <0>; bus-frequency = <0>; si1: si@700 { compatible = "fsl,t1040-qe-si"; reg = <0x700 0x80>; }; siram1: siram@1000 { compatible = "fsl,t1040-qe-siram"; reg = <0x1000 0x800>; }; ucc_hdlc: ucc@2000 { compatible = "fsl,ucc-hdlc"; rx-clock-name = "clk8"; tx-clock-name = "clk9"; fsl,rx-sync-clock = "rsync_pin"; fsl,tx-sync-clock = "tsync_pin"; fsl,tx-timeslot-mask = <0xfffffffe>; fsl,rx-timeslot-mask = <0xfffffffe>; fsl,tdm-framer-type = "e1"; fsl,tdm-id = <0>; fsl,siram-entry-id = <0>; fsl,tdm-interface; }; ucc_serial: ucc@2200 { compatible = "fsl,t1040-ucc-uart"; port-number = <0>; rx-clock-name = "brg2"; tx-clock-name = "brg2"; }; }; };