/* * Keymile KMETER1 Device Tree Source * * 2008-2011 DENX Software Engineering GmbH * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. */ /dts-v1/; / { model = "KMETER1"; compatible = "keymile,KMETER1"; #address-cells = <1>; #size-cells = <1>; aliases { ethernet0 = &enet_piggy2; ethernet1 = &enet_estar1; ethernet2 = &enet_estar2; ethernet3 = &enet_eth1; ethernet4 = &enet_eth2; ethernet5 = &enet_eth3; ethernet6 = &enet_eth4; serial0 = &serial0; }; cpus { #address-cells = <1>; #size-cells = <0>; PowerPC,8360@0 { device_type = "cpu"; reg = <0x0>; d-cache-line-size = <32>; // 32 bytes i-cache-line-size = <32>; // 32 bytes d-cache-size = <32768>; // L1, 32K i-cache-size = <32768>; // L1, 32K timebase-frequency = <0>; /* Filled in by U-Boot */ bus-frequency = <0>; /* Filled in by U-Boot */ clock-frequency = <0>; /* Filled in by U-Boot */ }; }; memory { device_type = "memory"; reg = <0 0>; /* Filled in by U-Boot */ }; soc8360@e0000000 { #address-cells = <1>; #size-cells = <1>; device_type = "soc"; compatible = "fsl,mpc8360-immr", "simple-bus"; ranges = <0x0 0xe0000000 0x00200000>; reg = <0xe0000000 0x00000200>; bus-frequency = <0>; /* Filled in by U-Boot */ pmc: power@b00 { compatible = "fsl,mpc8360-pmc", "fsl,mpc8349-pmc"; reg = <0xb00 0x100 0xa00 0x100>; interrupts = <80 0x8>; interrupt-parent = <&ipic>; }; i2c@3000 { #address-cells = <1>; #size-cells = <0>; cell-index = <0>; compatible = "fsl,mpc8313-i2c","fsl-i2c"; reg = <0x3000 0x100>; interrupts = <14 0x8>; interrupt-parent = <&ipic>; clock-frequency = <400000>; }; serial0: serial@4500 { cell-index = <0>; device_type = "serial"; compatible = "fsl,ns16550", "ns16550"; reg = <0x4500 0x100>; clock-frequency = <264000000>; interrupts = <9 0x8>; interrupt-parent = <&ipic>; }; dma@82a8 { #address-cells = <1>; #size-cells = <1>; compatible = "fsl,mpc8360-dma", "fsl,elo-dma"; reg = <0x82a8 4>; ranges = <0 0x8100 0x1a8>; interrupt-parent = <&ipic>; interrupts = <71 8>; cell-index = <0>; dma-channel@0 { compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; reg = <0 0x80>; interrupt-parent = <&ipic>; interrupts = <71 8>; }; dma-channel@80 { compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; reg = <0x80 0x80>; interrupt-parent = <&ipic>; interrupts = <71 8>; }; dma-channel@100 { compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; reg = <0x100 0x80>; interrupt-parent = <&ipic>; interrupts = <71 8>; }; dma-channel@180 { compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; reg = <0x180 0x28>; interrupt-parent = <&ipic>; interrupts = <71 8>; }; }; ipic: pic@700 { #address-cells = <0>; #interrupt-cells = <2>; compatible = "fsl,pq2pro-pic", "fsl,ipic"; interrupt-controller; reg = <0x700 0x100>; }; par_io@1400 { #address-cells = <1>; #size-cells = <0>; reg = <0x1400 0x100>; compatible = "fsl,mpc8360-par_io"; num-ports = <7>; qe_pio_c: gpio-controller@30 { #gpio-cells = <2>; compatible = "fsl,mpc8360-qe-pario-bank", "fsl,mpc8323-qe-pario-bank"; reg = <0x1430 0x18>; gpio-controller; }; pio_ucc1: ucc_pin@0 { reg = <0>; pio-map = < /* port pin dir open_drain assignment has_irq */ 0 1 3 0 2 0 /* MDIO */ 0 2 1 0 1 0 /* MDC */ 0 3 1 0 1 0 /* TxD0 */ 0 4 1 0 1 0 /* TxD1 */ 0 5 1 0 1 0 /* TxD2 */ 0 6 1 0 1 0 /* TxD3 */ 0 9 2 0 1 0 /* RxD0 */ 0 10 2 0 1 0 /* RxD1 */ 0 11 2 0 1 0 /* RxD2 */ 0 12 2 0 1 0 /* RxD3 */ 0 7 1 0 1 0 /* TX_EN */ 0 8 1 0 1 0 /* TX_ER */ 0 15 2 0 1 0 /* RX_DV */ 0 16 2 0 1 0 /* RX_ER */ 0 0 2 0 1 0 /* RX_CLK */ 2 9 1 0 3 0 /* GTX_CLK - CLK10 */ 2 8 2 0 1 0 /* GTX125 - CLK9 */ >; }; pio_ucc2: ucc_pin@1 { reg = <1>; pio-map = < /* port pin dir open_drain assignment has_irq */ 0 1 3 0 2 0 /* MDIO */ 0 2 1 0 1 0 /* MDC */ 0 17 1 0 1 0 /* TxD0 */ 0 18 1 0 1 0 /* TxD1 */ 0 19 1 0 1 0 /* TxD2 */ 0 20 1 0 1 0 /* TxD3 */ 0 23 2 0 1 0 /* RxD0 */ 0 24 2 0 1 0 /* RxD1 */ 0 25 2 0 1 0 /* RxD2 */ 0 26 2 0 1 0 /* RxD3 */ 0 21 1 0 1 0 /* TX_EN */ 0 22 1 0 1 0 /* TX_ER */ 0 29 2 0 1 0 /* RX_DV */ 0 30 2 0 1 0 /* RX_ER */ 0 31 2 0 1 0 /* RX_CLK */ 2 2 1 0 2 0 /* GTX_CLK - CLK3 */ 2 3 2 0 1 0 /* GTX125 - CLK4 */ >; }; pio_ucc4: ucc_pin@3 { reg = <3>; pio-map = < /* port pin dir open_drain assignment has_irq */ 0 1 3 0 2 0 /* MDIO */ 0 2 1 0 1 0 /* MDC */ 1 14 1 0 1 0 /* TxD0 (PB14, out, f1) */ 1 15 1 0 1 0 /* TxD1 (PB15, out, f1) */ 1 20 2 0 1 0 /* RxD0 (PB20, in, f1) */ 1 21 2 0 1 0 /* RxD1 (PB21, in, f1) */ 1 18 1 0 1 0 /* TX_EN (PB18, out, f1) */ 1 26 2 0 1 0 /* RX_DV (PB26, in, f1) */ 1 27 2 0 1 0 /* RX_ER (PB27, in, f1) */ 2 16 2 0 1 0 /* UCC4_RMII_CLK (CLK17) */ >; }; pio_ucc5: ucc_pin@4 { reg = <4>; pio-map = < /* port pin dir open_drain assignment has_irq */ 0 1 3 0 2 0 /* MDIO */ 0 2 1 0 1 0 /* MDC */ 3 0 1 0 1 0 /* TxD0 (PD0, out, f1) */ 3 1 1 0 1 0 /* TxD1 (PD1, out, f1) */ 3 6 2 0 1 0 /* RxD0 (PD6, in, f1) */ 3 7 2 0 1 0 /* RxD1 (PD7, in, f1) */ 3 4 1 0 1 0 /* TX_EN (PD4, out, f1) */ 3 12 2 0 1 0 /* RX_DV (PD12, in, f1) */ 3 13 2 0 1 0 /* RX_ER (PD13, in, f1) */ >; }; pio_ucc6: ucc_pin@5 { reg = <5>; pio-map = < /* port pin dir open_drain assignment has_irq */ 0 1 3 0 2 0 /* MDIO */ 0 2 1 0 1 0 /* MDC */ 3 14 1 0 1 0 /* TxD0 (PD14, out, f1) */ 3 15 1 0 1 0 /* TxD1 (PD15, out, f1) */ 3 20 2 0 1 0 /* RxD0 (PD20, in, f1) */ 3 21 2 0 1 0 /* RxD1 (PD21, in, f1) */ 3 18 1 0 1 0 /* TX_EN (PD18, out, f1) */ 3 26 2 0 1 0 /* RX_DV (PD26, in, f1) */ 3 27 2 0 1 0 /* RX_ER (PD27, in, f1) */ >; }; pio_ucc7: ucc_pin@6 { reg = <6>; pio-map = < /* port pin dir open_drain assignment has_irq */ 0 1 3 0 2 0 /* MDIO */ 0 2 1 0 1 0 /* MDC */ 4 0 1 0 1 0 /* TxD0 (PE0, out, f1) */ 4 1 1 0 1 0 /* TxD1 (PE1, out, f1) */ 4 6 2 0 1 0 /* RxD0 (PE6, in, f1) */ 4 7 2 0 1 0 /* RxD1 (PE7, in, f1) */ 4 4 1 0 1 0 /* TX_EN (PE4, out, f1) */ 4 12 2 0 1 0 /* RX_DV (PE12, in, f1) */ 4 13 2 0 1 0 /* RX_ER (PE13, in, f1) */ >; }; pio_ucc8: ucc_pin@7 { reg = <7>; pio-map = < /* port pin dir open_drain assignment has_irq */ 0 1 3 0 2 0 /* MDIO */ 0 2 1 0 1 0 /* MDC */ 4 14 1 0 2 0 /* TxD0 (PE14, out, f2) */ 4 15 1 0 1 0 /* TxD1 (PE15, out, f1) */ 4 20 2 0 1 0 /* RxD0 (PE20, in, f1) */ 4 21 2 0 1 0 /* RxD1 (PE21, in, f1) */ 4 18 1 0 1 0 /* TX_EN (PE18, out, f1) */ 4 26 2 0 1 0 /* RX_DV (PE26, in, f1) */ 4 27 2 0 1 0 /* RX_ER (PE27, in, f1) */ 2 15 2 0 1 0 /* UCCx_RMII_CLK (CLK16) */ >; }; }; qe@100000 { #address-cells = <1>; #size-cells = <1>; compatible = "fsl,qe"; ranges = <0x0 0x100000 0x100000>; reg = <0x100000 0x480>; clock-frequency = <0>; /* Filled in by U-Boot */ brg-frequency = <0>; /* Filled in by U-Boot */ bus-frequency = <0>; /* Filled in by U-Boot */ muram@10000 { #address-cells = <1>; #size-cells = <1>; compatible = "fsl,qe-muram", "fsl,cpm-muram"; ranges = <0x0 0x00010000 0x0000c000>; data-only@0 { compatible = "fsl,qe-muram-data", "fsl,cpm-muram-data"; reg = <0x0 0xc000>; }; }; /* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */ enet_estar1: ucc@2000 { device_type = "network"; compatible = "ucc_geth"; cell-index = <1>; reg = <0x2000 0x200>; interrupts = <32>; interrupt-parent = <&qeic>; local-mac-address = [ 00 00 00 00 00 00 ]; rx-clock-name = "none"; tx-clock-name = "clk9"; phy-handle = <&phy_estar1>; phy-connection-type = "rgmii-id"; pio-handle = <&pio_ucc1>; }; /* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */ enet_estar2: ucc@3000 { device_type = "network"; compatible = "ucc_geth"; cell-index = <2>; reg = <0x3000 0x200>; interrupts = <33>; interrupt-parent = <&qeic>; local-mac-address = [ 00 00 00 00 00 00 ]; rx-clock-name = "none"; tx-clock-name = "clk4"; phy-handle = <&phy_estar2>; phy-connection-type = "rgmii-id"; pio-handle = <&pio_ucc2>; }; /* Piggy2 (UCC4, MDIO 0x00, RMII) */ enet_piggy2: ucc@3200 { device_type = "network"; compatible = "ucc_geth"; cell-index = <4>; reg = <0x3200 0x200>; interrupts = <35>; interrupt-parent = <&qeic>; local-mac-address = [ 00 00 00 00 00 00 ]; rx-clock-name = "none"; tx-clock-name = "clk17"; phy-handle = <&phy_piggy2>; phy-connection-type = "rmii"; pio-handle = <&pio_ucc4>; }; /* Eth-1 (UCC5, MDIO 0x08, RMII) */ enet_eth1: ucc@2400 { device_type = "network"; compatible = "ucc_geth"; cell-index = <5>; reg = <0x2400 0x200>; interrupts = <40>; interrupt-parent = <&qeic>; local-mac-address = [ 00 00 00 00 00 00 ]; rx-clock-name = "none"; tx-clock-name = "clk16"; phy-handle = <&phy_eth1>; phy-connection-type = "rmii"; pio-handle = <&pio_ucc5>; }; /* Eth-2 (UCC6, MDIO 0x09, RMII) */ enet_eth2: ucc@3400 { device_type = "network"; compatible = "ucc_geth"; cell-index = <6>; reg = <0x3400 0x200>; interrupts = <41>; interrupt-parent = <&qeic>; local-mac-address = [ 00 00 00 00 00 00 ]; rx-clock-name = "none"; tx-clock-name = "clk16"; phy-handle = <&phy_eth2>; phy-connection-type = "rmii"; pio-handle = <&pio_ucc6>; }; /* Eth-3 (UCC7, MDIO 0x0a, RMII) */ enet_eth3: ucc@2600 { device_type = "network"; compatible = "ucc_geth"; cell-index = <7>; reg = <0x2600 0x200>; interrupts = <42>; interrupt-parent = <&qeic>; local-mac-address = [ 00 00 00 00 00 00 ]; rx-clock-name = "none"; tx-clock-name = "clk16"; phy-handle = <&phy_eth3>; phy-connection-type = "rmii"; pio-handle = <&pio_ucc7>; }; /* Eth-4 (UCC8, MDIO 0x0b, RMII) */ enet_eth4: ucc@3600 { device_type = "network"; compatible = "ucc_geth"; cell-index = <8>; reg = <0x3600 0x200>; interrupts = <43>; interrupt-parent = <&qeic>; local-mac-address = [ 00 00 00 00 00 00 ]; rx-clock-name = "none"; tx-clock-name = "clk16"; phy-handle = <&phy_eth4>; phy-connection-type = "rmii"; pio-handle = <&pio_ucc8>; }; mdio@3320 { #address-cells = <1>; #size-cells = <0>; reg = <0x3320 0x18>; compatible = "fsl,ucc-mdio"; /* Piggy2 (UCC4, MDIO 0x00, RMII) */ phy_piggy2: ethernet-phy@0 { reg = <0x0>; }; /* Eth-1 (UCC5, MDIO 0x08, RMII) */ phy_eth1: ethernet-phy@8 { reg = <0x08>; }; /* Eth-2 (UCC6, MDIO 0x09, RMII) */ phy_eth2: ethernet-phy@9 { reg = <0x09>; }; /* Eth-3 (UCC7, MDIO 0x0a, RMII) */ phy_eth3: ethernet-phy@a { reg = <0x0a>; }; /* Eth-4 (UCC8, MDIO 0x0b, RMII) */ phy_eth4: ethernet-phy@b { reg = <0x0b>; }; /* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */ phy_estar1: ethernet-phy@10 { interrupt-parent = <&ipic>; interrupts = <17 0x8>; reg = <0x10>; }; /* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */ phy_estar2: ethernet-phy@11 { interrupt-parent = <&ipic>; interrupts = <18 0x8>; reg = <0x11>; }; }; qeic: interrupt-controller@80 { interrupt-controller; compatible = "fsl,qe-ic"; #address-cells = <0>; #interrupt-cells = <1>; reg = <0x80 0x80>; big-endian; interrupts = < 32 0x8 33 0x8 34 0x8 35 0x8 40 0x8 41 0x8 42 0x8 43 0x8 >; interrupt-parent = <&ipic>; }; }; }; localbus@e0005000 { #address-cells = <2>; #size-cells = <1>; compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus", "simple-bus"; reg = <0xe0005000 0xd8>; ranges = <0 0 0xf0000000 0x04000000 /* LB 0 */ 1 0 0xe8000000 0x01000000 /* LB 1 */ 3 0 0xa0000000 0x10000000>; /* LB 3 */ flash@0,0 { compatible = "cfi-flash"; reg = <0 0 0x04000000>; #address-cells = <1>; #size-cells = <1>; bank-width = <2>; partition@0 { /* 768KB */ label = "u-boot"; reg = <0 0xC0000>; }; partition@c0000 { /* 128KB */ label = "env"; reg = <0xC0000 0x20000>; }; partition@e0000 { /* 128KB */ label = "envred"; reg = <0xE0000 0x20000>; }; partition@100000 { /* 64512KB */ label = "ubi0"; reg = <0x100000 0x3F00000>; }; }; }; };