/* * MPC8548CDS Device Tree Source stub (no addresses or top-level ranges) * * Copyright 2012 Freescale Semiconductor Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * Neither the name of Freescale Semiconductor nor the * names of its contributors may be used to endorse or promote products * derived from this software without specific prior written permission. * * * ALTERNATIVELY, this software may be distributed under the terms of the * GNU General Public License ("GPL") as published by the Free Software * Foundation, either version 2 of that License or (at your option) any * later version. * * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ &board_lbc { nor@0,0 { #address-cells = <1>; #size-cells = <1>; compatible = "cfi-flash"; reg = <0x0 0x0 0x01000000>; bank-width = <2>; device-width = <2>; partition@0 { reg = <0x0 0x0b00000>; label = "ramdisk-nor"; }; partition@300000 { reg = <0x0b00000 0x0400000>; label = "kernel-nor"; }; partition@700000 { reg = <0x0f00000 0x060000>; label = "dtb-nor"; }; partition@760000 { reg = <0x0f60000 0x020000>; label = "env-nor"; read-only; }; partition@780000 { reg = <0x0f80000 0x080000>; label = "u-boot-nor"; read-only; }; }; board-control@1,0 { compatible = "fsl,mpc8548cds-fpga"; reg = <0x1 0x0 0x1000>; }; }; &board_soc { i2c@3000 { eeprom@50 { compatible = "atmel,24c64"; reg = <0x50>; }; eeprom@56 { compatible = "atmel,24c64"; reg = <0x56>; }; eeprom@57 { compatible = "atmel,24c64"; reg = <0x57>; }; }; i2c@3100 { eeprom@50 { compatible = "atmel,24c64"; reg = <0x50>; }; }; enet0: ethernet@24000 { tbi-handle = <&tbi0>; phy-handle = <&phy0>; }; mdio@24520 { phy0: ethernet-phy@0 { interrupts = <5 1 0 0>; reg = <0x0>; }; phy1: ethernet-phy@1 { interrupts = <5 1 0 0>; reg = <0x1>; }; phy2: ethernet-phy@2 { interrupts = <5 1 0 0>; reg = <0x2>; }; phy3: ethernet-phy@3 { interrupts = <5 1 0 0>; reg = <0x3>; }; tbi0: tbi-phy@11 { reg = <0x11>; device_type = "tbi-phy"; }; }; enet1: ethernet@25000 { tbi-handle = <&tbi1>; phy-handle = <&phy1>; }; mdio@25520 { tbi1: tbi-phy@11 { reg = <0x11>; device_type = "tbi-phy"; }; }; enet2: ethernet@26000 { tbi-handle = <&tbi2>; phy-handle = <&phy2>; }; mdio@26520 { tbi2: tbi-phy@11 { reg = <0x11>; device_type = "tbi-phy"; }; }; enet3: ethernet@27000 { tbi-handle = <&tbi3>; phy-handle = <&phy3>; }; mdio@27520 { tbi3: tbi-phy@11 { reg = <0x11>; device_type = "tbi-phy"; }; }; }; &board_pci0 { interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x4 (PCIX Slot 2) */ 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0 /* IDSEL 0x5 (PCIX Slot 3) */ 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0 0x2800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0 0x2800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0 0x2800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0 /* IDSEL 0x6 (PCIX Slot 4) */ 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0 /* IDSEL 0x8 (PCIX Slot 5) */ 0x4000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0 0x4000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0 0x4000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0 0x4000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0 /* IDSEL 0xC (Tsi310 bridge) */ 0x6000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0 0x6000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0 0x6000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0 0x6000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0 /* IDSEL 0x14 (Slot 2) */ 0xa000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0 0xa000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0 0xa000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0 0xa000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0 /* IDSEL 0x15 (Slot 3) */ 0xa800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0 0xa800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0 0xa800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0 0xa800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0 /* IDSEL 0x16 (Slot 4) */ 0xb000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0 0xb000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0 0xb000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0 0xb000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0 /* IDSEL 0x18 (Slot 5) */ 0xc000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0 0xc000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0 0xc000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0 0xc000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0 /* IDSEL 0x1C (Tsi310 bridge PCI primary) */ 0xe000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0 0xe000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0 0xe000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0 0xe000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>; pci_bridge@1c { interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x00 (PrPMC Site) */ 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0 /* IDSEL 0x04 (VIA chip) */ 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0 /* IDSEL 0x05 (8139) */ 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0 /* IDSEL 0x06 (Slot 6) */ 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0 /* IDESL 0x07 (Slot 7) */ 0x3800 0x0 0x0 0x1 &mpic 0x3 0x1 0 0 0x3800 0x0 0x0 0x2 &mpic 0x0 0x1 0 0 0x3800 0x0 0x0 0x3 &mpic 0x1 0x1 0 0 0x3800 0x0 0x0 0x4 &mpic 0x2 0x1 0 0>; reg = <0xe000 0x0 0x0 0x0 0x0>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; ranges = <0x2000000 0x0 0x80000000 0x2000000 0x0 0x80000000 0x0 0x20000000 0x1000000 0x0 0x0 0x1000000 0x0 0x0 0x0 0x80000>; clock-frequency = <33333333>; isa@4 { device_type = "isa"; #interrupt-cells = <2>; #size-cells = <1>; #address-cells = <2>; reg = <0x2000 0x0 0x0 0x0 0x0>; ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>; interrupt-parent = <&i8259>; i8259: interrupt-controller@20 { interrupt-controller; device_type = "interrupt-controller"; reg = <0x1 0x20 0x2 0x1 0xa0 0x2 0x1 0x4d0 0x2>; #address-cells = <0>; #interrupt-cells = <2>; compatible = "chrp,iic"; interrupts = <0 1 0 0>; interrupt-parent = <&mpic>; }; rtc@70 { compatible = "pnpPNP,b00"; reg = <0x1 0x70 0x2>; }; }; }; };