// SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2019-20 Sean Anderson * Copyright (C) 2020 Western Digital Corporation or its affiliates. */ #include #include #include / { /* * Although the K210 is a 64-bit CPU, the address bus is only 32-bits * wide, and the upper half of all addresses is ignored. */ #address-cells = <1>; #size-cells = <1>; compatible = "canaan,kendryte-k210"; aliases { serial0 = &uarths0; serial1 = &uart1; serial2 = &uart2; serial3 = &uart3; }; /* * The K210 has an sv39 MMU following the privileged specification v1.9. * Since this is a non-ratified draft specification, the kernel does not * support it and the K210 support enabled only for the !MMU case. * Be consistent with this by setting the CPUs MMU type to "none". */ cpus { #address-cells = <1>; #size-cells = <0>; timebase-frequency = <7800000>; cpu0: cpu@0 { device_type = "cpu"; compatible = "canaan,k210", "riscv"; reg = <0>; riscv,isa = "rv64imafdc"; mmu-type = "riscv,none"; i-cache-block-size = <64>; i-cache-size = <0x8000>; d-cache-block-size = <64>; d-cache-size = <0x8000>; cpu0_intc: interrupt-controller { #interrupt-cells = <1>; interrupt-controller; compatible = "riscv,cpu-intc"; }; }; cpu1: cpu@1 { device_type = "cpu"; compatible = "canaan,k210", "riscv"; reg = <1>; riscv,isa = "rv64imafdc"; mmu-type = "riscv,none"; i-cache-block-size = <64>; i-cache-size = <0x8000>; d-cache-block-size = <64>; d-cache-size = <0x8000>; cpu1_intc: interrupt-controller { #interrupt-cells = <1>; interrupt-controller; compatible = "riscv,cpu-intc"; }; }; }; sram: memory@80000000 { device_type = "memory"; compatible = "canaan,k210-sram"; reg = <0x80000000 0x400000>, <0x80400000 0x200000>, <0x80600000 0x200000>; reg-names = "sram0", "sram1", "aisram"; clocks = <&sysclk K210_CLK_SRAM0>, <&sysclk K210_CLK_SRAM1>, <&sysclk K210_CLK_AI>; clock-names = "sram0", "sram1", "aisram"; }; clocks { in0: oscillator { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; }; soc { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; ranges; interrupt-parent = <&plic0>; rom0: nvmem@1000 { reg = <0x1000 0x1000>; read-only; }; clint0: timer@2000000 { compatible = "canaan,k210-clint", "sifive,clint0"; reg = <0x2000000 0xC000>; interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 &cpu1_intc 3 &cpu1_intc 7>; }; plic0: interrupt-controller@c000000 { #interrupt-cells = <1>; #address-cells = <0>; compatible = "canaan,k210-plic", "sifive,plic-1.0.0"; reg = <0xC000000 0x4000000>; interrupt-controller; interrupts-extended = <&cpu0_intc 11 &cpu1_intc 11>; riscv,ndev = <65>; }; uarths0: serial@38000000 { compatible = "canaan,k210-uarths", "sifive,uart0"; reg = <0x38000000 0x1000>; interrupts = <33>; clocks = <&sysclk K210_CLK_CPU>; }; gpio0: gpio-controller@38001000 { #interrupt-cells = <2>; #gpio-cells = <2>; compatible = "canaan,k210-gpiohs", "sifive,gpio0"; reg = <0x38001000 0x1000>; interrupt-controller; interrupts = <34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65>; gpio-controller; ngpios = <32>; }; dmac0: dma-controller@50000000 { compatible = "snps,axi-dma-1.01a"; reg = <0x50000000 0x1000>; interrupts = <27 28 29 30 31 32>; #dma-cells = <1>; clocks = <&sysclk K210_CLK_DMA>, <&sysclk K210_CLK_DMA>; clock-names = "core-clk", "cfgr-clk"; resets = <&sysrst K210_RST_DMA>; dma-channels = <6>; snps,dma-masters = <2>; snps,priority = <0 1 2 3 4 5>; snps,data-width = <5>; snps,block-size = <0x200000 0x200000 0x200000 0x200000 0x200000 0x200000>; snps,axi-max-burst-len = <256>; }; apb0: bus@50200000 { #address-cells = <1>; #size-cells = <1>; compatible = "simple-pm-bus"; ranges; clocks = <&sysclk K210_CLK_APB0>; gpio1: gpio@50200000 { #address-cells = <1>; #size-cells = <0>; compatible = "snps,dw-apb-gpio"; reg = <0x50200000 0x80>; clocks = <&sysclk K210_CLK_APB0>, <&sysclk K210_CLK_GPIO>; clock-names = "bus", "db"; resets = <&sysrst K210_RST_GPIO>; gpio1_0: gpio-port@0 { #gpio-cells = <2>; #interrupt-cells = <2>; compatible = "snps,dw-apb-gpio-port"; reg = <0>; interrupt-controller; interrupts = <23>; gpio-controller; ngpios = <8>; }; }; uart1: serial@50210000 { compatible = "snps,dw-apb-uart"; reg = <0x50210000 0x100>; interrupts = <11>; clocks = <&sysclk K210_CLK_UART1>, <&sysclk K210_CLK_APB0>; clock-names = "baudclk", "apb_pclk"; resets = <&sysrst K210_RST_UART1>; reg-io-width = <4>; reg-shift = <2>; dcd-override; dsr-override; cts-override; ri-override; }; uart2: serial@50220000 { compatible = "snps,dw-apb-uart"; reg = <0x50220000 0x100>; interrupts = <12>; clocks = <&sysclk K210_CLK_UART2>, <&sysclk K210_CLK_APB0>; clock-names = "baudclk", "apb_pclk"; resets = <&sysrst K210_RST_UART2>; reg-io-width = <4>; reg-shift = <2>; dcd-override; dsr-override; cts-override; ri-override; }; uart3: serial@50230000 { compatible = "snps,dw-apb-uart"; reg = <0x50230000 0x100>; interrupts = <13>; clocks = <&sysclk K210_CLK_UART3>, <&sysclk K210_CLK_APB0>; clock-names = "baudclk", "apb_pclk"; resets = <&sysrst K210_RST_UART3>; reg-io-width = <4>; reg-shift = <2>; dcd-override; dsr-override; cts-override; ri-override; }; spi2: spi@50240000 { compatible = "canaan,k210-spi"; spi-slave; reg = <0x50240000 0x100>; #address-cells = <0>; #size-cells = <0>; interrupts = <3>; clocks = <&sysclk K210_CLK_SPI2>, <&sysclk K210_CLK_APB0>; clock-names = "ssi_clk", "pclk"; resets = <&sysrst K210_RST_SPI2>; spi-max-frequency = <25000000>; }; i2s0: i2s@50250000 { compatible = "snps,designware-i2s"; reg = <0x50250000 0x200>; interrupts = <5>; clocks = <&sysclk K210_CLK_I2S0>; clock-names = "i2sclk"; resets = <&sysrst K210_RST_I2S0>; }; i2s1: i2s@50260000 { compatible = "snps,designware-i2s"; reg = <0x50260000 0x200>; interrupts = <6>; clocks = <&sysclk K210_CLK_I2S1>; clock-names = "i2sclk"; resets = <&sysrst K210_RST_I2S1>; }; i2s2: i2s@50270000 { compatible = "snps,designware-i2s"; reg = <0x50270000 0x200>; interrupts = <7>; clocks = <&sysclk K210_CLK_I2S2>; clock-names = "i2sclk"; resets = <&sysrst K210_RST_I2S2>; }; i2c0: i2c@50280000 { compatible = "snps,designware-i2c"; reg = <0x50280000 0x100>; interrupts = <8>; clocks = <&sysclk K210_CLK_I2C0>, <&sysclk K210_CLK_APB0>; clock-names = "ref", "pclk"; resets = <&sysrst K210_RST_I2C0>; }; i2c1: i2c@50290000 { compatible = "snps,designware-i2c"; reg = <0x50290000 0x100>; interrupts = <9>; clocks = <&sysclk K210_CLK_I2C1>, <&sysclk K210_CLK_APB0>; clock-names = "ref", "pclk"; resets = <&sysrst K210_RST_I2C1>; }; i2c2: i2c@502a0000 { compatible = "snps,designware-i2c"; reg = <0x502A0000 0x100>; interrupts = <10>; clocks = <&sysclk K210_CLK_I2C2>, <&sysclk K210_CLK_APB0>; clock-names = "ref", "pclk"; resets = <&sysrst K210_RST_I2C2>; }; fpioa: pinmux@502b0000 { compatible = "canaan,k210-fpioa"; reg = <0x502B0000 0x100>; clocks = <&sysclk K210_CLK_FPIOA>, <&sysclk K210_CLK_APB0>; clock-names = "ref", "pclk"; resets = <&sysrst K210_RST_FPIOA>; canaan,k210-sysctl-power = <&sysctl 108>; }; timer0: timer@502d0000 { compatible = "snps,dw-apb-timer"; reg = <0x502D0000 0x100>; interrupts = <14 15>; clocks = <&sysclk K210_CLK_TIMER0>, <&sysclk K210_CLK_APB0>; clock-names = "timer", "pclk"; resets = <&sysrst K210_RST_TIMER0>; }; timer1: timer@502e0000 { compatible = "snps,dw-apb-timer"; reg = <0x502E0000 0x100>; interrupts = <16 17>; clocks = <&sysclk K210_CLK_TIMER1>, <&sysclk K210_CLK_APB0>; clock-names = "timer", "pclk"; resets = <&sysrst K210_RST_TIMER1>; }; timer2: timer@502f0000 { compatible = "snps,dw-apb-timer"; reg = <0x502F0000 0x100>; interrupts = <18 19>; clocks = <&sysclk K210_CLK_TIMER2>, <&sysclk K210_CLK_APB0>; clock-names = "timer", "pclk"; resets = <&sysrst K210_RST_TIMER2>; }; }; apb1: bus@50400000 { #address-cells = <1>; #size-cells = <1>; compatible = "simple-pm-bus"; ranges; clocks = <&sysclk K210_CLK_APB1>; wdt0: watchdog@50400000 { compatible = "snps,dw-wdt"; reg = <0x50400000 0x100>; interrupts = <21>; clocks = <&sysclk K210_CLK_WDT0>, <&sysclk K210_CLK_APB1>; clock-names = "tclk", "pclk"; resets = <&sysrst K210_RST_WDT0>; }; wdt1: watchdog@50410000 { compatible = "snps,dw-wdt"; reg = <0x50410000 0x100>; interrupts = <22>; clocks = <&sysclk K210_CLK_WDT1>, <&sysclk K210_CLK_APB1>; clock-names = "tclk", "pclk"; resets = <&sysrst K210_RST_WDT1>; }; sysctl: syscon@50440000 { compatible = "canaan,k210-sysctl", "syscon", "simple-mfd"; reg = <0x50440000 0x100>; clocks = <&sysclk K210_CLK_APB1>; clock-names = "pclk"; sysclk: clock-controller { #clock-cells = <1>; compatible = "canaan,k210-clk"; clocks = <&in0>; }; sysrst: reset-controller { compatible = "canaan,k210-rst"; #reset-cells = <1>; }; reboot: syscon-reboot { compatible = "syscon-reboot"; regmap = <&sysctl>; offset = <48>; mask = <1>; value = <1>; }; }; }; apb2: bus@52000000 { #address-cells = <1>; #size-cells = <1>; compatible = "simple-pm-bus"; ranges; clocks = <&sysclk K210_CLK_APB2>; spi0: spi@52000000 { #address-cells = <1>; #size-cells = <0>; compatible = "canaan,k210-spi"; reg = <0x52000000 0x100>; interrupts = <1>; clocks = <&sysclk K210_CLK_SPI0>, <&sysclk K210_CLK_APB2>; clock-names = "ssi_clk", "pclk"; resets = <&sysrst K210_RST_SPI0>; reset-names = "spi"; spi-max-frequency = <25000000>; num-cs = <4>; reg-io-width = <4>; }; spi1: spi@53000000 { #address-cells = <1>; #size-cells = <0>; compatible = "canaan,k210-spi"; reg = <0x53000000 0x100>; interrupts = <2>; clocks = <&sysclk K210_CLK_SPI1>, <&sysclk K210_CLK_APB2>; clock-names = "ssi_clk", "pclk"; resets = <&sysrst K210_RST_SPI1>; reset-names = "spi"; spi-max-frequency = <25000000>; num-cs = <4>; reg-io-width = <4>; }; spi3: spi@54000000 { #address-cells = <1>; #size-cells = <0>; compatible = "snps,dwc-ssi-1.01a"; reg = <0x54000000 0x200>; interrupts = <4>; clocks = <&sysclk K210_CLK_SPI3>, <&sysclk K210_CLK_APB2>; clock-names = "ssi_clk", "pclk"; resets = <&sysrst K210_RST_SPI3>; reset-names = "spi"; /* Could possibly go up to 200 MHz */ spi-max-frequency = <100000000>; num-cs = <4>; reg-io-width = <4>; }; }; }; };