// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2020-2021 Microchip Technology Inc */

/dts-v1/;

#include "mpfs.dtsi"
#include "mpfs-icicle-kit-fabric.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>

/ {
	model = "Microchip PolarFire-SoC Icicle Kit";
	compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
		     "microchip,mpfs";

	aliases {
		ethernet0 = &mac1;
		serial0 = &mmuart0;
		serial1 = &mmuart1;
		serial2 = &mmuart2;
		serial3 = &mmuart3;
		serial4 = &mmuart4;
	};

	chosen {
		stdout-path = "serial1:115200n8";
	};

	leds {
		compatible = "gpio-leds";

		led-1 {
			gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
			color = <LED_COLOR_ID_RED>;
			label = "led1";
		};

		led-2 {
			gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>;
			color = <LED_COLOR_ID_RED>;
			label = "led2";
		};

		led-3 {
			gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
			color = <LED_COLOR_ID_AMBER>;
			label = "led3";
		};

		led-4 {
			gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
			color = <LED_COLOR_ID_AMBER>;
			label = "led4";
		};
	};

	ddrc_cache_lo: memory@80000000 {
		device_type = "memory";
		reg = <0x0 0x80000000 0x0 0x40000000>;
		status = "okay";
	};

	ddrc_cache_hi: memory@1040000000 {
		device_type = "memory";
		reg = <0x10 0x40000000 0x0 0x40000000>;
		status = "okay";
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		hss_payload: region@BFC00000 {
			reg = <0x0 0xBFC00000 0x0 0x400000>;
			no-map;
		};
	};
};

&core_pwm0 {
	status = "okay";
};

&gpio2 {
	interrupts = <53>, <53>, <53>, <53>,
		     <53>, <53>, <53>, <53>,
		     <53>, <53>, <53>, <53>,
		     <53>, <53>, <53>, <53>,
		     <53>, <53>, <53>, <53>,
		     <53>, <53>, <53>, <53>,
		     <53>, <53>, <53>, <53>,
		     <53>, <53>, <53>, <53>;
	status = "okay";
};

&i2c0 {
	status = "okay";
};

&i2c1 {
	status = "okay";
};

&i2c2 {
	status = "okay";
};

&mac0 {
	phy-mode = "sgmii";
	phy-handle = <&phy0>;
	status = "okay";
};

&mac1 {
	phy-mode = "sgmii";
	phy-handle = <&phy1>;
	status = "okay";

	phy1: ethernet-phy@9 {
		reg = <9>;
	};

	phy0: ethernet-phy@8 {
		reg = <8>;
	};
};

&mbox {
	status = "okay";
};

&mmc {
	bus-width = <4>;
	disable-wp;
	cap-sd-highspeed;
	cap-mmc-highspeed;
	mmc-ddr-1_8v;
	mmc-hs200-1_8v;
	sd-uhs-sdr12;
	sd-uhs-sdr25;
	sd-uhs-sdr50;
	sd-uhs-sdr104;
	status = "okay";
};

&mmuart1 {
	status = "okay";
};

&mmuart2 {
	status = "okay";
};

&mmuart3 {
	status = "okay";
};

&mmuart4 {
	status = "okay";
};

&pcie {
	status = "okay";
};

&qspi {
	status = "okay";
};

&refclk {
	clock-frequency = <125000000>;
};

&refclk_ccc {
	clock-frequency = <50000000>;
};

&rtc {
	status = "okay";
};

&spi0 {
	status = "okay";
};

&spi1 {
	status = "okay";
};

&syscontroller {
	status = "okay";
};

&syscontroller_qspi {
	/*
	 * The flash *is* there, but Icicle kits that have engineering sample
	 * silicon (write?) access to this flash to non-functional. The system
	 * controller itself can actually access it, but the MSS cannot write
	 * an image there. Instantiating a coreQSPI in the fabric & connecting
	 * it to the flash instead should work though. Pre-production or later
	 * silicon does not have this issue.
	 */
	status = "disabled";

	sys_ctrl_flash: flash@0 { // MT25QL01GBBB8ESF-0SIT
		compatible = "jedec,spi-nor";
		#address-cells = <1>;
		#size-cells = <1>;
		spi-max-frequency = <20000000>;
		spi-rx-bus-width = <1>;
		reg = <0>;
	};
};

&usb {
	status = "okay";
	dr_mode = "host";
};