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loadaddr 0x80000000
soc imx6
ivtofs 0x400
/* Enable all clocks */
wm 32 0x020c4068 0xffffffff
wm 32 0x020c406c 0xffffffff
wm 32 0x020c4070 0xffffffff
wm 32 0x020c4074 0xffffffff
wm 32 0x020c4078 0xffffffff
wm 32 0x020c407c 0xffffffff
wm 32 0x020c4080 0xffffffff
/* IOMUX */
/* DDR IO type */
wm 32 0x020E04B4 0x000C0000
wm 32 0x020E04AC 0x00000000
/* Clock */
wm 32 0x020E027C 0x00000030
/* Control */
wm 32 0x020E0250 0x00000030
wm 32 0x020E024C 0x00000030
wm 32 0x020E0490 0x00000030
wm 32 0x020E0288 0x00000030
wm 32 0x020E0270 0x00000000
wm 32 0x020E0260 0x00000030
wm 32 0x020E0264 0x00000030
wm 32 0x020E04A0 0x00000030
/* Data strobe */
wm 32 0x020E0494 0x00020000
wm 32 0x020E0280 0x00000030
wm 32 0x020E0284 0x00000030
/* Data */
wm 32 0x020E04B0 0x00020000
wm 32 0x020E0498 0x00000030
wm 32 0x020E04A4 0x00000030
wm 32 0x020E0244 0x00000030
wm 32 0x020E0248 0x00000030
/* DDR Controller registers */
wm 32 0x021B001C 0x00008000
wm 32 0x021B0800 0xA1390003
/* Calibration values */
wm 32 0x021B080C 0x00000000
wm 32 0x021B083C 0x413B013B
wm 32 0x021B0848 0x4040373E
wm 32 0x021B0850 0x40405954
wm 32 0x021B081C 0x33333333
wm 32 0x021B0820 0x33333333
wm 32 0x021B082C 0xf3333333
wm 32 0x021B0830 0xf3333333
/* END of calibration values */
wm 32 0x021B08C0 0x00921012
wm 32 0x021B08b8 0x00000800
/* MMDC init */
wm 32 0x021B0004 0x0002002D
wm 32 0x021B0008 0x1b333030
wm 32 0x021B000C 0x676B52F3
wm 32 0x021B0010 0xB66D0B63
wm 32 0x021B0014 0x01FF00DB
/* Consider reducing RALAT (currently set to 5) */
wm 32 0x021B0018 0x00201740
wm 32 0x021B001C 0x00008000
wm 32 0x021B002C 0x000026D2
wm 32 0x021B0030 0x006B1023
wm 32 0x021B0040 0x00000047
wm 32 0x021B0000 0x83180000
/* Mode registers writes for CS0 */
wm 32 0x021B001C 0x02008032
wm 32 0x021B001C 0x00008033
wm 32 0x021B001C 0x00048031
wm 32 0x021B001C 0x15208030
wm 32 0x021B001C 0x04008040
/* Final DDR setup */
wm 32 0x021B0020 0x00000800
wm 32 0x021B0818 0x00000227
wm 32 0x021B0004 0x0002552D
wm 32 0x021B0404 0x00011006
wm 32 0x021B001C 0x00000000
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