1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
|
#include <config.h>
#include <mach/imx-regs.h>
#define writel(val, reg) \
ldr r0, =reg; \
ldr r1, =val; \
str r1, [r0];
#if defined CONFIG_EUKREA_CPUIMX27_SDRAM_256MB
#define ROWS0 ESDCTL_ROW14
#define CFG0 0x0029572D
#elif defined CONFIG_EUKREA_CPUIMX27_SDRAM_128MB
#define ROWS0 ESDCTL_ROW13
#define CFG0 0x00095728
#endif
#define ESDCTL0_VAL (ESDCTL0_SDE | ROWS0 | ESDCTL0_COL10)
.macro sdram_init
/*
* DDR on CSD0
*/
writel(0x0000000C, ESDMISC) /* Enable DDR SDRAM operation */
writel(0x55555555, DSCR(3)) /* Set the driving strength */
writel(0x55555555, DSCR(5))
writel(0x55555555, DSCR(6))
writel(0x00005005, DSCR(7))
writel(0x15555555, DSCR(8))
writel(0x00000004, ESDMISC) /* Initial reset */
writel(CFG0, ESDCFG0)
writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE, ESDCTL0) /* precharge CSD0 all banks */
writel(0x00000000, 0xA0000F00) /* CSD0 precharge address (A10 = 1) */
writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH, ESDCTL0)
ldr r0, =0xa0000f00
mov r1, #0
mov r2, #8
1:
str r1, [r0]
subs r2, #1
bne 1b
writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE, ESDCTL0)
ldr r0, =0xA0000033
mov r1, #0xda
strb r1, [r0]
#if defined CONFIG_EUKREA_CPUIMX27_SDRAM_256MB
ldr r0, =0xA2000000
#elif defined CONFIG_EUKREA_CPUIMX27_SDRAM_128MB
ldr r0, =0xA1000000
#endif
mov r1, #0xff
strb r1, [r0]
writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 | ESDCTL0_BL | ESDCTL0_SMODE_NORMAL, ESDCTL0)
.endm
.section ".text_bare_init","ax"
.globl board_init_lowlevel
board_init_lowlevel:
mov r10, lr
/* ahb lite ip interface */
writel(0x20040304, AIPI1_PSR0)
writel(0xDFFBFCFB, AIPI1_PSR1)
writel(0x00000000, AIPI2_PSR0)
writel(0xFFFFFFFF, AIPI2_PSR1)
/* disable mpll/spll */
ldr r0, =CSCR
ldr r1, [r0]
bic r1, r1, #0x03
str r1, [r0]
/*
* pll clock initialization - see section 3.4.3 of the i.MX27 manual
*/
writel(0x00331C23, MPCTL0) /* MPLL = 399 MHz */
writel(0x040C2403, SPCTL0) /* SPLL = 240 MHz */
writel(0x33F38107 | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART, CSCR)
/* add some delay here */
mov r1, #0x1000
1: subs r1, r1, #0x1
bne 1b
/* clock gating enable */
writel(0x00050f08, GPCR)
/* peripheral clock divider */
writel(0x130400c3, PCDR0) /* FIXME */
writel(0x09030208, PCDR1) /* PERDIV1=08 @133 MHz */
/* PERDIV1=04 @266 MHz */
/* skip sdram initialization if we run from ram */
cmp pc, #0xa0000000
bls 1f
cmp pc, #0xc0000000
bhi 1f
mov pc,r10
1:
sdram_init
#ifdef CONFIG_NAND_IMX_BOOT
ldr sp, =0xa0f00000 /* Setup a temporary stack in SDRAM */
ldr r0, =IMX_NFC_BASE /* start of NFC SRAM */
ldr r2, =IMX_NFC_BASE + 0x1000 /* end of NFC SRAM */
/* skip NAND boot if not running from NFC space */
cmp pc, r0
bls ret
cmp pc, r2
bhi ret
/* Move ourselves out of NFC SRAM */
ldr r1, =TEXT_BASE
copy_loop:
ldmia r0!, {r3-r9} /* copy from source address [r0] */
stmia r1!, {r3-r9} /* copy to target address [r1] */
cmp r0, r2 /* until source end addreee [r2] */
ble copy_loop
ldr pc, =1f /* Jump to SDRAM */
1:
bl nand_boot /* Load barebox from NAND Flash */
ldr r1, =IMX_NFC_BASE - TEXT_BASE
sub r10, r10, r1 /* adjust return address from NFC SRAM */
/* to SDRAM */
#endif /* CONFIG_NAND_IMX_BOOT */
ret:
mov pc,r10
|
