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# SPDX-License-Identifier: GPL-2.0-only
soc imx7
loadaddr 0xbfbff000
ivtofs 0x400
#include <mach/imx7-ddr-regs.h>
wm 32 0x30340004 0x4F400005 /* IOMUXC_GPR_GPR1 */
/* Clear then set bit30 to ensure exit from DDR retention */
wm 32 0x30360388 0x40000000
wm 32 0x30360384 0x40000000
/* TQMa7x DRAM Timing REV0100 */
/* DCD Code i.MX7D/S 528 MHz 1 GByte Samsung K4B4G1646D */
wm 32 0x30360070 0x0070302C /* CCM_ANALOG_PLL_DDRx */
wm 32 0x30360090 0x00000000 /* CCM_ANALOG_PLL_NUM */
wm 32 0x30360070 0x0060302C /* CCM_ANALOG_PLL_DDRx */
check 32 until_all_bits_set 0x30360070 0x80000000
wm 32 0x30391000 0x00000002 /* SRC_DDRC_RCR */
wm 32 MX7_DDRC_MSTR 0x01040001
wm 32 MX7_DDRC_DFIUPD0 0x80400003
wm 32 MX7_DDRC_DFIUPD1 0x00100020
wm 32 MX7_DDRC_DFIUPD2 0x80100004
wm 32 MX7_DDRC_RFSHTMG 0x00200045
wm 32 MX7_DDRC_MP_PCTRL_0 0x00000001
wm 32 MX7_DDRC_INIT0 0x00020081
wm 32 MX7_DDRC_INIT1 0x00680000
wm 32 MX7_DDRC_INIT3 0x09300004
wm 32 MX7_DDRC_INIT4 0x00480000
wm 32 MX7_DDRC_INIT5 0x00100004
wm 32 MX7_DDRC_RANKCTL 0x0000033F
wm 32 MX7_DDRC_DRAMTMG0 0x090E0809
wm 32 MX7_DDRC_DRAMTMG1 0x0007020E
wm 32 MX7_DDRC_DRAMTMG2 0x03040407
wm 32 MX7_DDRC_DRAMTMG3 0x00002006
wm 32 MX7_DDRC_DRAMTMG4 0x04020304
wm 32 MX7_DDRC_DRAMTMG5 0x03030202
wm 32 MX7_DDRC_DRAMTMG8 0x00000803
wm 32 MX7_DDRC_ZQCTL0 0x00800020
wm 32 MX7_DDRC_DFITMG0 0x02098204
wm 32 MX7_DDRC_DFITMG1 0x00030303
wm 32 MX7_DDRC_ADDRMAP0 0x00000016
wm 32 MX7_DDRC_ADDRMAP1 0x00171717
wm 32 MX7_DDRC_ADDRMAP4 0x00000F0F
wm 32 MX7_DDRC_ADDRMAP5 0x04040404
wm 32 MX7_DDRC_ADDRMAP6 0x0F040404
wm 32 MX7_DDRC_ODTCFG 0x06000604
wm 32 MX7_DDRC_ODTMAP 0x00000001
wm 32 0x30391000 0x00000000 /* SRC_DDRC_RCR */
wm 32 MX7_DDR_PHY_PHY_CON0 0x17420F40
wm 32 MX7_DDR_PHY_PHY_CON1 0x10210100
wm 32 MX7_DDR_PHY_PHY_CON4 0x00060807
wm 32 MX7_DDR_PHY_MDLL_CON0 0x1010007E
wm 32 MX7_DDR_PHY_DRVDS_CON0 0x00000924
/* DDR_PHY_CMD_DESKEW_CON0 not set */
/* DDR_PHY_CMD_DESKEW_CON1 not set */
/* DDR_PHY_CMD_DESKEW_CON2 not set */
/* DDR_PHY_CMD_DESKEW_CON3 not set */
/* DDR_PHY_LVL_CON0 not set */
wm 32 MX7_DDR_PHY_OFFSET_RD_CON0 0x0B0B0B0B
wm 32 MX7_DDR_PHY_OFFSET_WR_CON0 0x06060606
wm 32 MX7_DDR_PHY_CMD_SDLL_CON0 0x01000010
wm 32 MX7_DDR_PHY_CMD_SDLL_CON0 0x00000010
wm 32 MX7_DDR_PHY_ZQ_CON0 0x0C407304
wm 32 MX7_DDR_PHY_ZQ_CON0 0x0C447304
wm 32 MX7_DDR_PHY_ZQ_CON0 0x0C447306
check 32 until_all_bits_set MX7_DDR_PHY_ZQ_CON1 0x1 /* ZQ Calibration is finished */
wm 32 MX7_DDR_PHY_ZQ_CON0 0x0C447304
wm 32 MX7_DDR_PHY_ZQ_CON0 0x0C407304
wm 32 0x30384130 0x00000000 /* CCM_CCGRn */
wm 32 0x30340020 0x00000178 /* IOMUXC_GPR_GPR8 */
wm 32 0x30384130 0x00000002 /* CCM_CCGRn */
wm 32 0x30790018 0x0000000f /* DDR_PHY_LP_CON0 */
/* DDRC_STAT */
check 32 until_all_bits_set 0x307a0004 0x1
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