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/* SPDX-License-Identifier: GPL-2.0-only */
soc imx6
loadaddr 0x10000000
ivtofs 0x400
#include "ddr3-defines.imxcfg"
/* Debug */
wm 32 0x020e0228 0x00000005
/* wm 32 0x020e0244 0x00000005 */
wm 32 0x020e05f8 0x000130b0
/* wm 32 0x020e0614 0x000130b0 */
#include "padsetup-q.imxcfg"
/* Set Read data delay 3 delay units for all bits */
wm 32 0x021b081c 0x33333333
wm 32 0x021b0820 0x33333333
wm 32 0x021b0824 0x33333333
wm 32 0x021b0828 0x33333333
wm 32 0x021b481c 0x33333333
wm 32 0x021b4820 0x33333333
wm 32 0x021b4824 0x33333333
wm 32 0x021b4828 0x33333333
/* MDMISC No addr mirror, 1 WALAT, 5 RALAT, DDR3 mode */
wm 32 0x021b0018 0x00001742
check 32 until_all_bits_clear 0x021b0018 0x00000002
/* CSCR: Configuration mode */
wm 32 0x021b001c 0x00008000
check 32 until_any_bit_set 0x021b001c 0x00004000
wm 32 0x021b000c MDCFG0_4G_533MHZ_CL7
wm 32 0x021b0010 MDCFG1_533MHZ
wm 32 0x021b0014 MDCFG2_533MHZ
/* MDRWD */
wm 32 0x021b002c 0x000026d2
wm 32 0x021b0030 MDOR_4G_533MHZ
wm 32 0x021b0008 MDOTC_533MHZ
wm 32 0x021b0004 MDPDC_533MHZ
wm 32 0x021b0040 MDASP_2GIB25
/* Dual-Plus specific configuration */
/* MMDC: MAARCR: Disable reordering */
wm 32 0x021b0400 0x14420000
/* MMDC: MPPDCMPR2: ZQ Offset setting (TODO) */
wm 32 0x021b0890 0x00400008 /* Freescale sabre-auto: 0x00400C58 */
/* NOC: DDRCONF */
/* Sabre-auto: wm 32 0x00bb0008 0x00000000 */
/* Values (Address mapping for 64bit):
* 0 : 16 Row, 3 Bank, 10 Col interleave (11 Col for 32 bit)
* 1 : 15 Row, 3 Bank, 11 Col interleave (12 Col for 32 bit)
* 2 : 18 Row, 3 Bank, 8 Col interleave (9 Col for 32 bit)
* 3 : 17 Row, 3 Bank, 9 Col interleave (10 Col for 32 bit)
* 4 : 2 CS (?), 15 Row, 3 Bank, 10 Col, interleave
* ...
*/
wm 32 0x00bb0008 0x00000000
/*
* NOC DdrTiming:
*
* Par. Chip VALUE SHIFT Reg. field
* ----------------------------------------------------------------
* ActToAct 533MHz 0x1b (28) 0 0x0000001b
* RdToMiss 533MHz 0x10 (16) 6 0x00000400
* WrToMiss * 0x1e (30) 12 0x0001e000
* BurstLen * 0x4 (8/2) 18 0x00100000
* RdToWr * 0x3 (3) 21 0x00600000
* WrToRd * 0xa (10) 26 0x28000000
* BwRatio * 0x0 (0) 31 0x00000000
* ----------------------------------------------------------------
*/
/* Sabre-auto: wm 32 0x00bb000c 0x2891E41A */
wm 32 0x00bb000c 0x2871e41c
/*
* NOC Activate:
*
* Par. Chip VALUE SHIFT Reg. field
* ----------------------------------------------------------------
* Rrd * 0x6 (6) 0 0x00000006
* Faw * 0x1b (27) 4 0x000001b0
* FawBank * 0x0 (0) 10 0x00000000
* ----------------------------------------------------------------
*/
/* Sabre-auto: wm 32 0x00bb0038 0x00000564 */
wm 32 0x00bb0038 0x000001b6
/*
* NOC ReadLatency: (FIXME)
*/
wm 32 0x00bb0014 0x00000040
/*
* NOC IPU1/IPU2 aging: (FIXME)
*/
wm 32 0x00bb0028 0x00000020
wm 32 0x00bb002c 0x00000020
wm 32 0x021b0000 MDCTL_4G
// check 32 until_any_bit_set 0x021b0018 0x80000000
/* DDR3 MR config */
wm 32 0x021b001c DDR3_MR2_533MHZ_RTT_120
/*
* DDR3 chip MR3, n = 3, vvvv = 0 (no configurable function of interest).
*/
wm 32 0x021b001c 0x00008033
wm 32 0x021b001c DDR3_MR1_RTT_120_ODS_40
wm 32 0x021b001c DDR3_MR0_533MHZ_CL7
/*
* ZQ calibration, n = 0x10 (Precharge all):
* Bit 10 = 1: Start ZQ calibration
* REGISTER: 0x04008040
*/
wm 32 0x021b001c 0x04008040
/* MPZQHWCTRL */
wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3 force calibration */
wm 32 0x021b4800 0xa1390003
wm 32 0x021b0020 MDREF_64KHZ
wm 32 0x021b0818 MPODTCTRL_ODT_60
wm 32 0x021b4818 MPODTCTRL_ODT_60
wm 32 0x021b083c MPDGCTRL0_CH0_533MHZ
wm 32 0x021b483c MPDGCTRL0_CH1_533MHZ
wm 32 0x021b0840 MPDGCTRL1_CH0_533MHZ
wm 32 0x021b4840 MPDGCTRL1_CH1_533MHZ
/* MPRDDLCTL, MPWRDLCTL */
wm 32 0x021b0848 0x40404040 /* TODO. Read delay line conf. */
wm 32 0x021b4848 0x40404040 /* For now set all to 50%. */
wm 32 0x021b0850 0x40404040
wm 32 0x021b4850 0x40404040
/* MPWLDECTRL0,1 */
wm 32 0x021b080c 0x001f001f /* TODO. Write level delay control */
wm 32 0x021b0810 0x001f001f
wm 32 0x021b480c 0x001f001f
wm 32 0x021b4810 0x001f001f
/* MPMUR0 */
wm 32 0x021b08b8 0x00000800 /* Force measurement on delay lines */
wm 32 0x021b48b8 0x00000800
/* MDSCR */
wm 32 0x021b001c 0x00000000 /* Disable configuration req */
/* MAPSR */
wm 32 0x021b0404 0x00001006 /* Enable autorefresh */
/* enable AXI cache for VDOA/PCIe/VPU/IPU */
wm 32 0x020e0010 0xff0000cf
/* set IPU AXI-id0 Qos=0xf(bypass AXI-id1 Qos=0x7) */
wm 32 0x020e0018 0x007f007f
wm 32 0x020e001c 0x007f007f
/* DEBUG leds */
wm 32 0x020e0244 0x00000005
wm 32 0x020e0614 0x000130b0
/* RGMII config */
wm 32 0x020e0790 0x00080000 /* 1V2 DDR IO */
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