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path: root/arch/arm/boards/reflex-achilles/pll-config-arria10.c
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#include <mach/arria10-clock-manager.h>

static struct arria10_mainpll_cfg mainpll_cfg = {
	.cntr15clk_cnt = 900,
	.cntr2clk_cnt = 900,
	.cntr3clk_cnt = 900,
	.cntr4clk_cnt = 900,
	.cntr5clk_cnt = 900,
	.cntr6clk_cnt = 7,
	.cntr7clk_cnt = 900,
	.cntr7clk_src = 0,
	.cntr8clk_cnt = 900,
	.cntr9clk_cnt = 900,
	.cntr9clk_src = 0,
	.mpuclk_cnt = 0,
	.mpuclk_src = 0,
	.nocclk_cnt = 0,
	.nocclk_src = 0,
	.nocdiv_csatclk = 2,
	.nocdiv_cspdbgclk = 0,
	.nocdiv_cstraceclk = 0,
	.nocdiv_l4mainclk = 2,
	.nocdiv_l4mpclk = 2,
	.nocdiv_l4spclk = 2,
	.vco0_psrc = 0,
	.vco1_denom = 1,
	.vco1_numer = 127,
	.mpuclk = 0x3840001,
	.nocclk = 0x3840003,
};

static struct arria10_perpll_cfg perpll_cfg = {
	.cntr2clk_cnt = 5,
	.cntr2clk_src = 1,
	.cntr3clk_cnt = 900,
	.cntr3clk_src = 1,
	.cntr4clk_cnt = 14,
	.cntr4clk_src = 1,
	.cntr5clk_cnt = 374,
	.cntr5clk_src = 1,
	.cntr6clk_cnt = 900,
	.cntr6clk_src = 0,
	.cntr7clk_cnt = 900,
	.cntr8clk_cnt = 900,
	.cntr8clk_src = 0,
	.cntr9clk_cnt = 900,
	.emacctl_emac0sel = 0,
	.emacctl_emac1sel = 0,
	.emacctl_emac2sel = 0,
	.gpiodiv_gpiodbclk = 32000,
	.vco0_psrc = 0,
	.vco1_denom = 1,
	.vco1_numer = 119,
};