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/*
* Copyright 2018 CogentEmbedded, Inc.
* Copyright 2011 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <arm/nxp/imx/imx51-zii-rdu1.dts>
/ {
compatible = "zii,imx51-rdu1", "fsl,imx51-babbage-power", "fsl,imx51";
chosen {
stdout-path = &uart1;
environment-spi {
compatible = "barebox,environment";
device-path = &env_spinor;
};
ubootenv {
compatible = "barebox,uboot-environment";
device-path = &uboot_env;
};
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
/* Address will be determined by the bootloader */
ramoops@afe00000 {
compatible = "ramoops";
reg = <0xafe00000 0x200000>;
ecc-size = <16>;
record-size = <0x20000>;
console-size = <0x20000>;
ftrace-size = <0x20000>;
pmsg-size = <0x20000>;
};
};
aliases {
/*
* NVMEM device corresponding to EEPROM attached to
* the switch shared DT node with it, so we use that
* fact to create a desirable naming
*/
switch-eeprom = &{mdio_gpio/switch@0};
microwire-eeprom = &{spi_gpio/eeprom@0};
};
};
spinor: &{ecspi1/flash@1} {
partition@0 {
/*
* Do not change the size of this
* partition. RDU1's BBU code relies on
* "barebox" partition starting at 1024 byte
* mark to function properly
*/
label = "config";
reg = <0x0 0x400>;
};
partition@400 {
label = "barebox";
reg = <0x400 0xdfc00>;
};
env_spinor: partition@e0000 {
label = "barebox-environment";
reg = <0xe0000 0x20000>;
};
};
&esdhc1 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/*
* Layout info is taken from /etc/fw_env.config
*/
uboot_env: partition@c0000 {
label = "uboot-environment";
reg = <0xc0000 0x20000>;
};
};
};
&{uart3/mcu/watchdog} {
nvmem-cells = <&boot_source>;
nvmem-cell-names = "boot-source";
};
&{uart3/mcu/eeprom@a4} {
nvmem-cells = <&shadow_config>;
nvmem-cell-names = "shadow-config";
boot_source: boot-source@83 {
reg = <0x83 1>;
};
shadow_config: shadow-config@1000 {
reg = <0x1000 0x400>;
};
};
&fec {
status = "disabled";
};
&pinctrl_usbh1 {
/*
* Overwrite upstream USBH1,2 iomux settings to match
* the setting U-Boot would set these to. Remove this
* once this is fixed upstream.
*/
fsl,pins = <
MX51_PAD_USBH1_STP__USBH1_STP 0x1e5
MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5
MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5
MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5
MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5
MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5
MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5
MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5
MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5
MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5
MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5
MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5
>;
};
&pinctrl_usbh2 {
fsl,pins = <
MX51_PAD_EIM_A26__USBH2_STP 0x1e5
MX51_PAD_EIM_A24__USBH2_CLK 0x1e5
MX51_PAD_EIM_A25__USBH2_DIR 0x1e5
MX51_PAD_EIM_A27__USBH2_NXT 0x1e5
MX51_PAD_EIM_D16__USBH2_DATA0 0x1e5
MX51_PAD_EIM_D17__USBH2_DATA1 0x1e5
MX51_PAD_EIM_D18__USBH2_DATA2 0x1e5
MX51_PAD_EIM_D19__USBH2_DATA3 0x1e5
MX51_PAD_EIM_D20__USBH2_DATA4 0x1e5
MX51_PAD_EIM_D21__USBH2_DATA5 0x1e5
MX51_PAD_EIM_D22__USBH2_DATA6 0x1e5
MX51_PAD_EIM_D23__USBH2_DATA7 0x1e5
>;
};
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