path: root/arch/arm/dts/imx6q-guf-santaro.dts

/*
 * Copyright 2014 Sascha Hauer <s.hauer@pengutronix.de>
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http:/*www.opensource.org/licenses/gpl-license.html
 * http:/*www.gnu.org/copyleft/gpl.html
 */

/dts-v1/;

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <arm/imx6q.dtsi>
#include "imx6q.dtsi"

/ {
	model = "Garz+Fricke i.MX6q Santaro";
	compatible = "guf,imx6q-santaro", "fsl,imx6q";

	memory {
		reg = <0x10000000 0x40000000>;
	};

	chosen {
		stdout-path = &uart2;

		environment-emmc {
			compatible = "barebox,environment";
			device-path = &usdhc4, "partname:boot1";
		};
	};

	reg_backlight: reg_backlight {
		compatible = "regulator-fixed";
		regulator-name = "3P3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio5 22 0>;
		enable-active-high;
	};

	backlight: backlight {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_backlight>;
		compatible = "pwm-backlight";
		pwms = <&pwm1 0 5000000>;
		brightness-levels = <0 4 8 16 32 64 128 255>;
		default-brightness-level = <7>;
		power-supply = <&reg_backlight>;
		status = "okay";
	};

	phyclk: phyclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <25000000>;
	};

	panel {
		compatible = "simple-panel";
		backlight = <&backlight>;
		enable-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
		enable-delay = <200>;

		port {
			panel_in: endpoint {
				remote-endpoint = <&lvds0_out>;
			};
		};
	};
};

&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet>;
	phy-mode = "rmii";
	status = "okay";
	clocks = <&clks IMX6QDL_CLK_ENET>,
		 <&clks IMX6QDL_CLK_ENET>,
		 <&phyclk>;
};

&i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	eeprom: m24c64@50 {
		compatible = "st,24c32", "at24";
		reg = <0x50>;
	};

	pmic: pf0100@08 {
		status = "disabled";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_pmic>;
		compatible = "pf0100-regulator";
		reg = <0x08>;
		interrupt-parent = <&gpio7>;
		interrupts = <13 8>;

		regulators {
			reg_vddcore: sw1ab {
				regulator-min-microvolt = <300000>;
				regulator-max-microvolt = <1875000>;
				regulator-always-on;
			};

			reg_vddsoc: sw1c {
				regulator-min-microvolt = <300000>;
				regulator-max-microvolt = <1875000>;
				regulator-always-on;
			};

			reg_gen_3v3: sw2 {
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};

			reg_ddr_1v5a: sw3a {
				regulator-min-microvolt = <400000>;
				regulator-max-microvolt = <1975000>;
				regulator-always-on;
			};

			reg_ddr_1v5b: sw3b {
				regulator-min-microvolt = <400000>;
				regulator-max-microvolt = <1975000>;
				regulator-always-on;
			};

			reg_ddr_vtt: sw4 {
				regulator-min-microvolt = <400000>;
				regulator-max-microvolt = <1975000>;
				regulator-always-on;
			};

			reg_5v_600mA: swbst {
				regulator-min-microvolt = <5000000>;
				regulator-max-microvolt = <5150000>;
				regulator-always-on;
			};

			reg_snvs_3v: vsnvs {
				regulator-min-microvolt = <1500000>;
				regulator-max-microvolt = <3000000>;
				regulator-always-on;
			};

			reg_vrefddr: vrefddr {
				regulator-min-microvolt = <750000>;
				regulator-max-microvolt = <750000>;
				regulator-always-on;
			};

			reg_vgen1_1v5: vgen1 {
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1550000>;
				/* not used */
			};

			reg_vgen2_1v2_eth: vgen2 {
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1550000>;
				regulator-always-on;
			};

			reg_vgen3_2v8: vgen3 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};

			reg_vgen4_1v8: vgen4 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};

			reg_vgen5_1v8_eth: vgen5 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};

			reg_vgen6_3v3: vgen6 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};
		};
	};

	codec: sgtl5000@0a {
		compatible = "fsl,sgtl5000";
		reg = <0x0a>;
		clocks = <&clks 201>;
	};

	rtc@51 {
		compatible = "nxp,pcf8563";
		reg = <0x51>;
	};

	temp@49 {
		compatible = "ti,lm73";
		reg = <0x49>;
	};
};

&i2c3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";

	polytouch: edt-ft5x06@38 {
		compatible = "edt,edt-ft5206";
		reg = <0x38>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_touch>;
		interrupt-parent = <&gpio4>;
		interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
		reset-gpios = <&gpio1 20 1>;
		wake-gpios = <&gpio1 18 0>;
		edt,threshold = <30>;
		edt,gain = <3>;
		edt,offset = <0>;
		edt,report-rate = <8>;
	};
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	imx6qdl-santaro {
		pinctrl_hog: hoggrp {
			fsl,pins = <
				MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07		0x80000000 /* ATDETECT */
				MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08		0x80000000 /* EXTPWR */
				MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18		0x80000000 /* LED1 */
				MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31		0x80000000 /* CLEAR_ALL */
				MX6QDL_PAD_GPIO_9__WDOG1_B			0x80000000 /* WDT_OUTPUT */
				MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29		0x80000000 /* RTC_INT */
				MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28		0x80000000 /* TALERT */
				MX6QDL_PAD_SD3_DAT2__GPIO7_IO06			0x80000000 /* KP5V_OC */
				MX6QDL_PAD_SD3_DAT3__GPIO7_IO07			0x80000000 /* KP5V_PWR */
				MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30		0x80000000 /* PFO_12V */

				MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24		0x80000000 /* DIG_IN1 */
				MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23		0x80000000 /* DIG_IN2 */
				MX6QDL_PAD_SD1_DAT1__GPIO1_IO17			0x80000000 /* DIG_OUT1 */
				MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25		0x80000000 /* DIG_OUT2 */

				MX6QDL_PAD_SD3_DAT3__GPIO7_IO07			0x80000000 /* KP_5V0 */
			>;
		};

		pinctrl_audio: audiogrp {
			fsl,pins = <
				MX6QDL_PAD_DISP0_DAT20__AUD4_TXC		0x80000000
				MX6QDL_PAD_DISP0_DAT21__AUD4_TXD		0x80000000
				MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS		0x80000000
				MX6QDL_PAD_DISP0_DAT23__AUD4_RXD		0x80000000
				MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1			0x80000000 /* SGTL500 sys_mclk */
				MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29		0x80000000 /* SPEAKER_ON */
			>;
		};

		pinctrl_display: displaygrp {
			fsl,pins = <
				/* LVDS-GPIO */
				MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21		0x80000000 /* LCD_ENABLE */
				MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20		0x80000000 /* SEL6_8 */
			>;
		};

		pinctrl_backlight: backlightgrp {
			fsl,pins = <
				MX6QDL_PAD_SD1_DAT3__PWM1_OUT			0x80000000 /* BL-PWM-Out */
				MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22		0x80000000 /* BL-ON */
			>;
		};

		pinctrl_i2c1: i2c1grp {
			fsl,pins = <
				/* I2C1	(internal) */
				MX6QDL_PAD_CSI0_DAT8__I2C1_SDA			0x4001b8b1
				MX6QDL_PAD_CSI0_DAT9__I2C1_SCL			0x4001b8b1
			>;
		};

		pinctrl_i2c3: i2c3grp {
			fsl,pins = <
				/* I2C3  (HDMI-DCC, ResTOUCH, CTOUCH ) */
				MX6QDL_PAD_GPIO_5__I2C3_SCL			0x4001b8b1
				MX6QDL_PAD_GPIO_6__I2C3_SDA			0x4001b8b1
			>;
		};

		pinctrl_touch: touchgrp {
			fsl,pins = <
				MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26		0x80000000 /* CTOUCH_INT2 */
				MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27		0x80000000 /* CTOUCH_INT */
				MX6QDL_PAD_SD1_CMD__GPIO1_IO18			0x80000000 /* CTOUCH_RESET2 */
				MX6QDL_PAD_SD1_CLK__GPIO1_IO20			0x80000000 /* CTOUCH_RESET */
				MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06		0x80000000 /* ResTOUCH_INT */
			>;
		};

		pinctrl_ecspi2: ecspi2grp {
			fsl,pins = <
				/* CTOUCH */
				MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI		0x80000000
				MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO		0x80000000
				MX6QDL_PAD_DISP0_DAT18__ECSPI2_SS0		0x80000000
				MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK		0x80000000
				MX6QDL_PAD_EIM_A25__ECSPI2_RDY			0x80000000
			>;
		};

		pinctrl_can1: can1grp {
			fsl,pins = <
				MX6QDL_PAD_GPIO_7__FLEXCAN1_TX			0x80000000
				MX6QDL_PAD_GPIO_8__FLEXCAN1_RX			0x80000000
			>;
		};

		pinctrl_can2: can2grp {
			fsl,pins = <
				MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX		0x80000000
				MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX		0x80000000
			>;
		};


		pinctrl_uart1: uart1grp {
			fsl,pins = <
				MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA		0x1b0b1
				MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA		0x1b0b1
				MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09		0x1b0b1 /* CAN/RS485_PWR_EN */
				MX6QDL_PAD_SD3_RST__GPIO7_IO08			0x1b0b1 /* RS485_DE */
			>;
		};

		pinctrl_uart2: uart2grp {
			fsl,pins = <
				MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA		0x1b0b1
				MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA		0x1b0b1
				MX6QDL_PAD_SD3_CMD__UART2_CTS_B			0x1b0b1
				MX6QDL_PAD_SD3_CLK__UART2_RTS_B			0x1b0b1
			>;
		};

		pinctrl_uart4: uart4grp {
			fsl,pins = <
				MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA		0x1b0b1
				MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA		0x1b0b1
				MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B		0x1b0b1
				MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B		0x1b0b1
			>;
		};

		pinctrl_uart5: uart5grp {
			fsl,pins = <
				MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA		0x1b0b1
				MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA		0x1b0b1
				MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B		0x1b0b1
				MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B		0x1b0b1
				MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28		0x1b0b1 /* uC_MDB_WakeUpOut */
			>;
		};

		pinctrl_usdhc2: usdhc2grp {
			fsl,pins = <
				MX6QDL_PAD_SD2_CLK__SD2_CLK			0x80000000
				MX6QDL_PAD_SD2_CMD__SD2_CMD			0x80000000
				MX6QDL_PAD_SD2_DAT0__SD2_DATA0			0x80000000
				MX6QDL_PAD_SD2_DAT1__SD2_DATA1			0x80000000
				MX6QDL_PAD_SD2_DAT2__SD2_DATA2			0x80000000
				MX6QDL_PAD_SD2_DAT3__SD2_DATA3			0x80000000
				MX6QDL_PAD_GPIO_2__GPIO1_IO02			0x80000000
				MX6QDL_PAD_GPIO_4__GPIO1_IO04			0x80000000
			>;
		};

		pinctrl_usdhc4: usdhc4grp {
			fsl,pins = <
				MX6QDL_PAD_SD4_CLK__SD4_CLK			0x80000000
				MX6QDL_PAD_SD4_CMD__SD4_CMD			0x80000000
				MX6QDL_PAD_SD4_DAT0__SD4_DATA0			0x80000000
				MX6QDL_PAD_SD4_DAT1__SD4_DATA1			0x80000000
				MX6QDL_PAD_SD4_DAT2__SD4_DATA2			0x80000000
				MX6QDL_PAD_SD4_DAT3__SD4_DATA3			0x80000000
				MX6QDL_PAD_SD4_DAT4__SD4_DATA4			0x80000000
				MX6QDL_PAD_SD4_DAT5__SD4_DATA5			0x80000000
				MX6QDL_PAD_SD4_DAT6__SD4_DATA6			0x80000000
				MX6QDL_PAD_SD4_DAT7__SD4_DATA7			0x80000000
			>;
		};

		pinctrl_enet: enetgrp {
			fsl,pins = <
				MX6QDL_PAD_ENET_MDIO__ENET_MDIO			0x1b0b0
				MX6QDL_PAD_ENET_MDC__ENET_MDC			0x1b0b0
				MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN		0x1b0b0
				MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER		0x1b0b0
				MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN		0x1b0b0
				MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0		0x1b0b0
				MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1		0x1b0b0
				MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0		0x1b0b0
				MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1		0x1b0b0
				MX6QDL_PAD_GPIO_16__ENET_REF_CLK		0x1b0b0 /* REF_CLK (in) */
				MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23		0x1b0b0 /* FEC_INT */
			>;
		};

		pinctrl_usbh1: usbh1grp {
			fsl,pins = <
				MX6QDL_PAD_GPIO_0__USB_H1_PWR			0x80000000
				MX6QDL_PAD_GPIO_3__USB_H1_OC			0x80000000
				MX6QDL_PAD_SD1_DAT0__GPIO1_IO16			0x80000000 /* USB_HUB_CONNECT */
				MX6QDL_PAD_GPIO_17__GPIO7_IO12			0x80000000 /* USB_HUB_INT */
			>;
		};

		pinctrl_usbh2: usbh2grp {
			fsl,pins = <
				MX6QDL_PAD_RGMII_TXC__USB_H2_DATA		0x80000000 /* USBH2_DATA */
				MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE		0x80000000 /* USBH2_STROBE */
			>;
		};

		pinctrl_usboth: usbotggrp {
			fsl,pins = <
				MX6QDL_PAD_KEY_COL4__USB_OTG_OC			0x80000000
				MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR		0x80000000
				MX6QDL_PAD_GPIO_1__USB_OTG_ID			0x80000000
			>;
		};

		pinctrl_pmic: pmicgrp {
			fsl,pins = <
				MX6QDL_PAD_GPIO_18__GPIO7_IO13			0x80000000 /* PMIC_INT_B */
			>;
		};

		pinctrl_pfid: pfidgrp {
			fsl,pins = <
				MX6QDL_PAD_NANDF_D0__GPIO2_IO00			0x80000000 /* PFID0 */
				MX6QDL_PAD_NANDF_D1__GPIO2_IO01			0x80000000 /* PFID1 */
				MX6QDL_PAD_NANDF_D2__GPIO2_IO02			0x80000000 /* PFID2 */
				MX6QDL_PAD_NANDF_D3__GPIO2_IO03			0x80000000 /* PFID3 */
				MX6QDL_PAD_NANDF_D4__GPIO2_IO04			0x80000000 /* PFID4 */
				MX6QDL_PAD_NANDF_D5__GPIO2_IO05			0x80000000 /* PFID5 */
				MX6QDL_PAD_NANDF_D6__GPIO2_IO06			0x80000000 /* PFID6 */
				MX6QDL_PAD_NANDF_D7__GPIO2_IO07			0x80000000 /* PFID7 */
			>;
		};

		pinctrl_sram: sramgrp {
			fsl,pins = <
				MX6QDL_PAD_EIM_CS0__EIM_CS0_B			0x80000000
				MX6QDL_PAD_EIM_DA0__EIM_AD00			0x80000000
				MX6QDL_PAD_EIM_DA1__EIM_AD01			0x80000000
				MX6QDL_PAD_EIM_DA2__EIM_AD02			0x80000000
				MX6QDL_PAD_EIM_DA3__EIM_AD03			0x80000000
				MX6QDL_PAD_EIM_DA4__EIM_AD04			0x80000000
				MX6QDL_PAD_EIM_DA5__EIM_AD05			0x80000000
				MX6QDL_PAD_EIM_DA6__EIM_AD06			0x80000000
				MX6QDL_PAD_EIM_DA7__EIM_AD07			0x80000000
				MX6QDL_PAD_EIM_DA8__EIM_AD08			0x80000000
				MX6QDL_PAD_EIM_DA9__EIM_AD09			0x80000000
				MX6QDL_PAD_EIM_DA10__EIM_AD10			0x80000000
				MX6QDL_PAD_EIM_DA11__EIM_AD11			0x80000000
				MX6QDL_PAD_EIM_DA12__EIM_AD12			0x80000000
				MX6QDL_PAD_EIM_DA13__EIM_AD13			0x80000000
				MX6QDL_PAD_EIM_DA14__EIM_AD14			0x80000000
				MX6QDL_PAD_EIM_DA15__EIM_AD15			0x80000000
				MX6QDL_PAD_EIM_A16__EIM_ADDR16			0x80000000
				MX6QDL_PAD_EIM_A17__EIM_ADDR17			0x80000000
				MX6QDL_PAD_EIM_A18__EIM_ADDR18			0x80000000
				MX6QDL_PAD_EIM_A19__EIM_ADDR19			0x80000000
				MX6QDL_PAD_EIM_A20__EIM_ADDR20			0x80000000
				MX6QDL_PAD_EIM_D16__EIM_DATA16			0x80000000
				MX6QDL_PAD_EIM_D17__EIM_DATA17			0x80000000
				MX6QDL_PAD_EIM_D18__EIM_DATA18			0x80000000
				MX6QDL_PAD_EIM_D19__EIM_DATA19			0x80000000
				MX6QDL_PAD_EIM_D20__EIM_DATA20			0x80000000
				MX6QDL_PAD_EIM_D21__EIM_DATA21			0x80000000
				MX6QDL_PAD_EIM_D22__EIM_DATA22			0x80000000
				MX6QDL_PAD_EIM_D23__EIM_DATA23			0x80000000
				MX6QDL_PAD_EIM_D24__EIM_DATA24			0x80000000
				MX6QDL_PAD_EIM_D25__EIM_DATA25			0x80000000
				MX6QDL_PAD_EIM_D26__EIM_DATA26			0x80000000
				MX6QDL_PAD_EIM_D27__EIM_DATA27			0x80000000
				MX6QDL_PAD_EIM_D28__EIM_DATA28			0x80000000
				MX6QDL_PAD_EIM_D29__EIM_DATA29			0x80000000
				MX6QDL_PAD_EIM_D30__EIM_DATA30			0x80000000
				MX6QDL_PAD_EIM_D31__EIM_DATA31			0x80000000
			>;
		};
	};
};

&ldb {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_display>;

	lvds-channel@0 {
		status = "okay";
		fsl,data-mapping = "spwg";
		fsl,data-width = <18>;

		display-timings {
			timing0: 800x480 {
				clock-frequency = <35338240>;
				hactive = <800>;
				vactive = <480>;
				hfront-porch = <100>;
				hback-porch = <100>;
				hsync-len = <24>;
				hsync-active = <1>;
				vfront-porch = <5>;
				vback-porch = <5>;
				vsync-len = <3>;
				vsync-active = <1>;
			};
		};

		port@4 {
			reg = <4>;
			lvds0_out: endpoint {
				remote-endpoint = <&panel_in>;
			};
		};
	};
};

&pwm1 {
	status = "okay";
};

&uart1 {
	/* RS485 */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

&uart2 {
	/* RS232 debug port */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	fsl,uart-has-rtscts;
	status = "okay";
};

&uart4 {
	/* TTL internal */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart4>;
	fsl,uart-has-rtscts;
	status = "okay";
};

&uart5 {
	/* RS232 MDB */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart5>;
	fsl,uart-has-rtscts;
	status = "okay";
};

&usbh1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbh1>;
	status = "okay";
};

&usbotg {
	status = "okay";
};

&usdhc2 {
	/* SD card socket */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2>;
	bus-width = <4>;
	cd-gpios = <&gpio1 4 0>;
	wp-gpios = <&gpio1 2 0>;
	status = "okay";
	#address-cells = <1>;
	#size-cells = <1>;

	partition@e0000 {
		label = "barebox-environment";
		reg = <0xe0000 0x20000>;
	};
};

&usdhc4 {
	/* eMMC */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc4>;
	bus-width = <8>;
	non-removable;
	status = "okay";
};