summaryrefslogtreecommitdiffstats
path: root/arch/arm/dts/imx6q-phytec-pfla02.dtsi
blob: 402eee804d6ff62d297853a5da776e87dbf3b141 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
/*
 * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include "imx6q.dtsi"

/ {
	model = "Phytec phyFLEX-i.MX6 Ouad";
	compatible = "phytec,imx6q-pfla02", "fsl,imx6q";

	memory {
		reg = <0x10000000 0x40000000>;
	};
};

&ecspi3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi3>;
	status = "okay";
	fsl,spi-num-chipselects = <1>;
	cs-gpios = <&gpio4 24 0>;

	flash: m25p80@0 {
		compatible = "m25p80";
		spi-max-frequency = <20000000>;
		reg = <0>;
	};
};

&i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	eeprom@50 {
		compatible = "atmel,24c32";
		reg = <0x50>;
	};

	pmic@58 {
		compatible = "dialog,da9063";
		reg = <0x58>;
		interrupt-parent = <&gpio4>;
		interrupts = <17 0x8>; /* active-low GPIO4_17 */

		regulators {
			vddcore_reg: bcore1 {
				regulator-min-microvolt = <730000>;
				regulator-max-microvolt = <1380000>;
				regulator-always-on;
			};

			vddsoc_reg: bcore2 {
				regulator-min-microvolt = <730000>;
				regulator-max-microvolt = <1380000>;
				regulator-always-on;
			};

			vdd_ddr3_reg: bpro {
				regulator-min-microvolt = <1500000>;
				regulator-max-microvolt = <1500000>;
				regulator-always-on;
			};

			vdd_3v3_reg: bperi {
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};

			vdd_buckmem_reg: bmem {
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};

			vdd_eth_reg: bio {
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <1200000>;
				regulator-always-on;
			};

			vdd_eth_io_reg: ldo4 {
				regulator-min-microvolt = <2500000>;
				regulator-max-microvolt = <2500000>;
				regulator-always-on;
			};

			vdd_mx6_snvs_reg: ldo5 {
				regulator-min-microvolt = <3000000>;
				regulator-max-microvolt = <3000000>;
				regulator-always-on;
			};

			vdd_3v3_pmic_io_reg: ldo6 {
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};

			vdd_sd0_reg: ldo9 {
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
			};

			vdd_sd1_reg: ldo10 {
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
			};

			vdd_mx6_high_reg: ldo11 {
				regulator-min-microvolt = <3000000>;
				regulator-max-microvolt = <3000000>;
				regulator-always-on;
			};
		};
	};
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	imx6q-phytec-pfla02 {
		pinctrl_hog: hoggrp {
			fsl,pins = <
				MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
				MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */
				MX6QDL_PAD_DI0_PIN15__GPIO4_IO17  0x80000000 /* PMIC interrupt */
			>;
		};

		pinctrl_ecspi3: ecspi3grp {
			fsl,pins = <MX6QDL_ECSPI3_PINGRP1>;
		};

		pinctrl_enet: enetgrp {
			fsl,pins = <MX6QDL_ENET_PINGRP3>;
		};

		pinctrl_gpmi_nand: gpmigrp {
			fsl,pins = <MX6QDL_GPMI_NAND_PINGRP1>;
		};

		pinctrl_i2c1: i2c1grp {
			fsl,pins = <MX6QDL_I2C1_PINGRP1>;
		};

		pinctrl_uart4: uart4grp {
			fsl,pins = <MX6QDL_UART4_PINGRP1>;
		};

		pinctrl_usdhc2: usdhc2grp {
			fsl,pins = <MX6QDL_USDHC2_PINGRP_D4>;
		};

		pinctrl_usdhc3: usdhc3grp {
			fsl,pins = <MX6QDL_USDHC3_PINGRP_D4>;
		};

		pinctrl_usdhc3_cdwp: usdhc3cdwp {
			fsl,pins = <
				MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
				MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
			>;
		};
	};
};

&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet>;
	phy-mode = "rgmii";
	phy-reset-gpios = <&gpio3 23 0>;
	status = "disabled";
};

&flash {
	#address-cells = <1>;
	#size-cells = <1>;

	partition@0 {
		label = "barebox";
		reg = <0x0 0x80000>;
	};

	partition@1 {
		label = "barebox-environment";
		reg = <0x80000 0x10000>;
	};
};

&gpmi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpmi_nand>;
	nand-on-flash-bbt;
	status = "okay";
	#address-cells = <1>;
	#size-cells = <1>;

	partition@0 {
		label = "barebox";
		reg = <0x0 0x200000>;
	};

	partition@1 {
		label = "ubi";
		reg = <0x200000 0x3fe00000>;
	};
};

&ocotp {
	barebox,provide-mac-address = <&fec 0x620>;
};

&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart4>;
	status = "disabled";
};

&usdhc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2>;
	cd-gpios = <&gpio1 4 0>;
	wp-gpios = <&gpio1 2 0>;
	status = "disabled";
};

&usdhc3 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_usdhc3
		     &pinctrl_usdhc3_cdwp>;
        cd-gpios = <&gpio1 27 0>;
        wp-gpios = <&gpio1 29 0>;
        status = "disabled";
};