1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
|
/*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <init.h>
#include <common.h>
#include <io.h>
#include <sizes.h>
#include <mach/generic.h>
#include <mach/revision.h>
#include <mach/imx6-regs.h>
#include <mach/generic.h>
#define SI_REV 0x260
void imx6_init_lowlevel(void)
{
void __iomem *aips1 = (void *)MX6_AIPS1_ON_BASE_ADDR;
void __iomem *aips2 = (void *)MX6_AIPS2_ON_BASE_ADDR;
/*
* Set all MPROTx to be non-bufferable, trusted for R/W,
* not forced to user-mode.
*/
writel(0x77777777, aips1);
writel(0x77777777, aips1 + 0x4);
writel(0, aips1 + 0x40);
writel(0, aips1 + 0x44);
writel(0, aips1 + 0x48);
writel(0, aips1 + 0x4c);
writel(0, aips1 + 0x50);
writel(0x77777777, aips2);
writel(0x77777777, aips2 + 0x4);
writel(0, aips2 + 0x40);
writel(0, aips2 + 0x44);
writel(0, aips2 + 0x48);
writel(0, aips2 + 0x4c);
writel(0, aips2 + 0x50);
/* enable all clocks */
writel(0xffffffff, 0x020c4068);
writel(0xffffffff, 0x020c406c);
writel(0xffffffff, 0x020c4070);
writel(0xffffffff, 0x020c4074);
writel(0xffffffff, 0x020c4078);
writel(0xffffffff, 0x020c407c);
writel(0xffffffff, 0x020c4080);
}
int imx6_init(void)
{
u32 rev;
u32 mx6_silicon_revision;
imx6_boot_save_loc((void *)MX6_SRC_BASE_ADDR);
rev = readl(MX6_ANATOP_BASE_ADDR + SI_REV);
switch (rev & 0xff) {
case 0x00:
mx6_silicon_revision = IMX_CHIP_REV_1_0;
break;
case 0x01:
mx6_silicon_revision = IMX_CHIP_REV_1_1;
break;
case 0x02:
mx6_silicon_revision = IMX_CHIP_REV_1_2;
break;
default:
mx6_silicon_revision = IMX_CHIP_REV_UNKNOWN;
}
imx_set_silicon_revision("i.MX6", mx6_silicon_revision);
return 0;
}
int imx6_devices_init(void)
{
add_generic_device("imx-iomuxv3", 0, NULL, MX6_IOMUXC_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx6-ccm", 0, NULL, MX6_CCM_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL);
add_generic_device("imx31-gpt", 0, NULL, MX6_GPT_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
add_generic_device("imx31-gpio", 0, NULL, MX6_GPIO1_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL);
add_generic_device("imx31-gpio", 1, NULL, MX6_GPIO2_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL);
add_generic_device("imx31-gpio", 2, NULL, MX6_GPIO3_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL);
add_generic_device("imx31-gpio", 3, NULL, MX6_GPIO4_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL);
add_generic_device("imx31-gpio", 4, NULL, MX6_GPIO5_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL);
add_generic_device("imx31-gpio", 5, NULL, MX6_GPIO6_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL);
add_generic_device("imx31-gpio", 6, NULL, MX6_GPIO7_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL);
add_generic_device("imx21-wdt", 0, NULL, MX6_WDOG1_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL);
add_generic_device("imx6-usb-misc", 0, NULL, MX6_USBOH3_USB_BASE_ADDR + 0x800, 0x100, IORESOURCE_MEM, NULL);
return 0;
}
|