summaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-imx/include/mach/imx8m-regs.h
blob: a5017faf830e90dad6b0660486473586b75e13e7 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
/* SPDX-License-Identifier: GPL-2.0-only */

#ifndef __MACH_IMX8M_REGS_H
#define __MACH_IMX8M_REGS_H

#define MX8M_GPIO1_BASE_ADDR		0X30200000
#define MX8M_GPIO2_BASE_ADDR		0x30210000
#define MX8M_GPIO3_BASE_ADDR		0x30220000
#define MX8M_GPIO4_BASE_ADDR		0x30230000
#define MX8M_GPIO5_BASE_ADDR		0x30240000
#define MX8M_WDOG1_BASE_ADDR		0x30280000
#define MX8M_WDOG2_BASE_ADDR		0x30290000
#define MX8M_WDOG3_BASE_ADDR		0x302A0000
#define MX8M_IOMUXC_BASE_ADDR		0x30330000
#define MX8M_IOMUXC_GPR_BASE_ADDR	0x30340000
#define MX8M_OCOTP_BASE_ADDR		0x30350000
#define MX8M_ANATOP_BASE_ADDR		0x30360000
#define MX8M_CCM_BASE_ADDR		0x30380000
#define MX8M_SRC_BASE_ADDR		0x30390000
#define MX8M_SRC_DDRC_RCR_ADDR		0x30391000
#define MX8M_GPC_BASE_ADDR		0x303A0000
#define MX8M_SYSCNT_CTRL_BASE_ADDR	0x306C0000
#define MX8M_UART1_BASE_ADDR		0x30860000
#define MX8M_UART3_BASE_ADDR		0x30880000
#define MX8M_UART2_BASE_ADDR		0x30890000
#define MX8M_I2C1_BASE_ADDR		0x30A20000
#define MX8M_I2C2_BASE_ADDR		0x30A30000
#define MX8M_I2C3_BASE_ADDR		0x30A40000
#define MX8M_I2C4_BASE_ADDR		0x30A50000
#define MX8M_UART4_BASE_ADDR		0x30A60000
#define MX8M_USDHC1_BASE_ADDR		0x30B40000
#define MX8M_USDHC2_BASE_ADDR		0x30B50000
#define MX8M_TZASC_BASE_ADDR		0x32f80000
#define MX8M_DDRC_PHY_BASE_ADDR		0x3c000000
#define MX8M_DDRC_DDR_SS_GPR0		(MX8M_DDRC_PHY_BASE_ADDR + 0x01000000)
#define MX8M_DDRC_IPS_BASE_ADDR(X)	(0x3d400000 + ((X) * 0x2000000))
#define MX8M_DDRC_CTL_BASE_ADDR		MX8M_DDRC_IPS_BASE_ADDR(0)
#define MX8M_DDR_CSD1_BASE_ADDR		0x40000000

#endif /* __MACH_IMX8M_REGS_H */