blob: f56c3f724e509ff30eb7697a66edd04e2a54ea8d (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
|
/*
* Atheros AR71XX/AR724X/AR913X SoC register definitions
*
* Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
* Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
*
* Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#ifndef __ASM_MACH_AR71XX_REGS_H
#define __ASM_MACH_AR71XX_REGS_H
#ifndef __ASSEMBLER__
#include <linux/bitops.h>
#else
#define BIT(nr) (1 << (nr))
#endif
#define AR71XX_APB_BASE 0x18000000
#define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000)
#define AR71XX_DDR_CTRL_SIZE 0x100
#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000)
#define AR71XX_GPIO_SIZE 0x100
#define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000)
#define AR71XX_PLL_SIZE 0x100
#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
#define AR71XX_RESET_SIZE 0x100
#define AR71XX_RTC_BASE (AR71XX_APB_BASE + 0x00107000)
#define AR71XX_RTC_SIZE 0x100
#define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)
#define AR933X_UART_SIZE 0x14
#define AR934X_UART0_BASE (AR71XX_APB_BASE + 0x00020000)
#define AR934X_UART0_SIZE 0x18
#define AR934X_UART0_SHIFT 2
/* WASP BootStrap Register */
#define WASP_BOOTSTRAP_REG (AR71XX_RESET_BASE + 0xb0)
#define WASP_REF_CLK_25 (1 << 4) /* 0 - 25MHz 1 - 40 MHz */
#define WASP_RAM_TYPE(a) ((a) & 0x3)
/*
* RTC block
*/
#define AR933X_RTC_REG_RESET 0x40
#define AR933X_RTC_REG_STATUS 0x44
#define AR933X_RTC_REG_DERIVED 0x48
#define AR933X_RTC_REG_FORCE_WAKE 0x4c
#define AR933X_RTC_REG_INT_CAUSE 0x50
#define AR933X_RTC_REG_CAUSE_CLR 0x50
#define AR933X_RTC_REG_INT_ENABLE 0x54
#define AR933X_RTC_REG_INT_MASKE 0x58
/*
* DDR_CTRL block
*/
#define AR933X_DDR_CONFIG 0x00
#define AR933X_DDR_CONFIG2 0x04
#define AR933X_DDR_MODE 0x08
#define AR933X_DDR_EXT_MODE 0x0c
#define AR933X_DDR_CTRL 0x10
#define AR933X_DDR_REFRESH 0x14
#define AR933X_DDR_RD_DATA 0x18
#define AR933X_DDR_TAP_CTRL0 0x1c
#define AR933X_DDR_TAP_CTRL1 0x20
#define AR933X_DDR_TAP_CTRL1 0x20
#define AR933X_DDR_DDR_DDR2_CONFIG 0x8c
#define AR933X_DDR_DDR_EMR2 0x90
#define AR933X_DDR_DDR_EMR3 0x94
/*
* GPIO block
*/
#define AR71XX_GPIO_REG_OE 0x00
#define AR71XX_GPIO_REG_IN 0x04
#define AR71XX_GPIO_REG_OUT 0x08
#define AR71XX_GPIO_REG_SET 0x0c
#define AR71XX_GPIO_REG_CLEAR 0x10
#define AR71XX_GPIO_REG_INT_MODE 0x14
#define AR71XX_GPIO_REG_INT_TYPE 0x18
#define AR71XX_GPIO_REG_INT_POLARITY 0x1c
#define AR71XX_GPIO_REG_INT_PENDING 0x20
#define AR71XX_GPIO_REG_INT_ENABLE 0x24
#define AR71XX_GPIO_REG_FUNC 0x28
/* Warning! GPIO_FUNC[15] must be written with 1 */
#define AR933X_GPIO_FUNC_RSRV15 BIT(15)
#define AR933X_GPIO_FUNC_UART_EN BIT(1)
/*
* PLL block
*/
#define AR933X_PLL_CPU_CONFIG_REG 0x00
#define AR933X_PLL_CPU_CONFIG2_REG 0x04
#define AR933X_PLL_CLOCK_CTRL_REG 0x08
#define AR933X_PLL_DITHER_FRAC_REG 0x10
#define AR933X_PLL_DITHER_REG 0x14
#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10
#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f
#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16
#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23
#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
#define AR933X_PLL_CPU_CONFIG_PLLPWD BIT(30)
#define AR933X_PLL_CLOCK_CTRL_BYPASS BIT(2)
#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT 5
#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK 0x3
#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT 10
#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK 0x3
#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15
#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7
/*
* RESET block
*/
#define AR933X_RESET_REG_RESET_MODULE 0x1c
#define AR933X_RESET_REG_BOOTSTRAP 0xac
#define AR71XX_RESET_FULL_CHIP BIT(24)
#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
#endif /* __ASM_MACH_AR71XX_REGS_H */
|
