1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
*/
#include <common.h>
#include <clock.h>
#include <linux/list.h>
#include <linux/clk.h>
#include <linux/clk/at91_pmc.h>
#include <mfd/syscon.h>
#include <regmap.h>
#include "pmc.h"
#define MASTER_SOURCE_MAX 4
#define MASTER_PRES_MASK 0x7
#define MASTER_PRES_MAX MASTER_PRES_MASK
#define MASTER_DIV_SHIFT 8
#define MASTER_DIV_MASK 0x3
#define to_clk_master(clk) container_of(clk, struct clk_master, clk)
struct clk_master {
struct clk clk;
struct regmap *regmap;
const struct clk_master_layout *layout;
const struct clk_master_characteristics *characteristics;
const char *parents[MASTER_SOURCE_MAX];
};
static inline bool clk_master_ready(struct regmap *regmap)
{
unsigned int status;
regmap_read(regmap, AT91_PMC_SR, &status);
return status & AT91_PMC_MCKRDY ? 1 : 0;
}
static int clk_master_enable(struct clk *clk)
{
struct clk_master *master = to_clk_master(clk);
while (!clk_master_ready(master->regmap))
barrier();
return 0;
}
static int clk_master_is_enabled(struct clk *clk)
{
struct clk_master *master = to_clk_master(clk);
return clk_master_ready(master->regmap);
}
static unsigned long clk_master_recalc_rate(struct clk *clk,
unsigned long parent_rate)
{
u8 pres;
u8 div;
unsigned long rate = parent_rate;
struct clk_master *master = to_clk_master(clk);
const struct clk_master_layout *layout = master->layout;
const struct clk_master_characteristics *characteristics =
master->characteristics;
unsigned int mckr;
regmap_read(master->regmap, AT91_PMC_MCKR, &mckr);
mckr &= layout->mask;
pres = (mckr >> layout->pres_shift) & MASTER_PRES_MASK;
div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
if (characteristics->have_div3_pres && pres == MASTER_PRES_MAX)
rate /= 3;
else
rate >>= pres;
rate /= characteristics->divisors[div];
if (rate < characteristics->output.min)
pr_warn("master clk is underclocked");
else if (rate > characteristics->output.max)
pr_warn("master clk is overclocked");
return rate;
}
static int clk_master_get_parent(struct clk *clk)
{
struct clk_master *master = to_clk_master(clk);
unsigned int mckr;
regmap_read(master->regmap, AT91_PMC_MCKR, &mckr);
return mckr & AT91_PMC_CSS;
}
static const struct clk_ops master_ops = {
.enable = clk_master_enable,
.is_enabled = clk_master_is_enabled,
.recalc_rate = clk_master_recalc_rate,
.get_parent = clk_master_get_parent,
};
struct clk *
at91_clk_register_master(struct regmap *regmap,
const char *name, int num_parents,
const char **parent_names,
const struct clk_master_layout *layout,
const struct clk_master_characteristics *characteristics)
{
int ret;
const size_t parent_names_size = num_parents * sizeof(parent_names[0]);
struct clk_master *master;
if (!name || !num_parents || !parent_names)
return ERR_PTR(-EINVAL);
master = xzalloc(sizeof(*master));
master->clk.name = name;
master->clk.ops = &master_ops;
memcpy(master->parents, parent_names, parent_names_size);
master->clk.parent_names = master->parents;
master->clk.num_parents = num_parents;
master->layout = layout;
master->characteristics = characteristics;
master->regmap = regmap;
ret = clk_register(&master->clk);
if (ret) {
kfree(master);
return ERR_PTR(ret);
}
return &master->clk;
}
const struct clk_master_layout at91rm9200_master_layout = {
.mask = 0x31F,
.pres_shift = 2,
};
const struct clk_master_layout at91sam9x5_master_layout = {
.mask = 0x373,
.pres_shift = 4,
};
|
