summaryrefslogtreecommitdiffstats
path: root/drivers/mci/s3c.c
blob: 773c84ad091ddfbbd1e5f95b2698edb0a55f4c57 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
/*
 * Copyright (C) 2010 Juergen Beisert <juergen@kreuzholzen.de>
 *
 * This code is partially based on u-boot code:
 *
 * This code is based on various Linux and u-boot sources:
 *  Copyright (C) 2004-2006 maintech GmbH, Thomas Kleffel <tk@maintech.de>
 *  Copyright (C) 2008 Simtec Electronics <ben-linux@fluff.org>
 *  (C) Copyright 2006 by OpenMoko, Inc.
 *  Author: Harald Welte <laforge@openmoko.org>
 *  based on u-boot pxa MMC driver and linux/drivers/mmc/s3c2410mci.c
 *  (C) 2005-2005 Thomas Kleffel
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

/**
 * @file
 * @brief MCI card host interface for S3C2440 CPU
 */

/* #define DEBUG */

#include <common.h>
#include <init.h>
#include <mci.h>
#include <errno.h>
#include <clock.h>
#include <io.h>
#include <mach/s3c-mci.h>
#include <mach/s3c-generic.h>
#include <mach/s3c-iomap.h>

#define GET_HOST_DATA(x) (x->priv)
#define GET_MCI_PDATA(x) (x->platform_data)

#define SDICON 0x0
# define SDICON_SDRESET (1 << 8)
# define SDICON_MMCCLOCK (1 << 5) /* this is a clock type SD or MMC style WTF? */
# define SDICON_BYTEORDER (1 << 4)
# define SDICON_SDIOIRQ (1 << 3)
# define SDICON_RWAITEN (1 << 2)
# define SDICON_FIFORESET (1 << 1) /* reserved bit on 2440 ????? */
# define SDICON_CLKEN (1 << 0) /* enable/disable external clock */

#define SDIPRE 0x4

#define SDICMDARG 0x8

#define SDICMDCON 0xc
# define SDICMDCON_ABORT (1 << 12)
# define SDICMDCON_WITHDATA (1 << 11)
# define SDICMDCON_LONGRSP (1 << 10)
# define SDICMDCON_WAITRSP (1 << 9)
# define SDICMDCON_CMDSTART (1 << 8)
# define SDICMDCON_SENDERHOST (1 << 6)
# define SDICMDCON_INDEX (0x3f)

#define SDICMDSTAT 0x10
# define SDICMDSTAT_CRCFAIL (1 << 12)
# define SDICMDSTAT_CMDSENT (1 << 11)
# define SDICMDSTAT_CMDTIMEOUT (1 << 10)
# define SDICMDSTAT_RSPFIN (1 << 9)
# define SDICMDSTAT_XFERING (1 << 8)
# define SDICMDSTAT_INDEX (0xff)

#define SDIRSP0 0x14
#define SDIRSP1 0x18
#define SDIRSP2 0x1C
#define SDIRSP3 0x20

#define SDITIMER 0x24
#define SDIBSIZE 0x28

#define SDIDCON 0x2c
# define SDIDCON_DS_BYTE (0 << 22)
# define SDIDCON_DS_HALFWORD (1 << 22)
# define SDIDCON_DS_WORD (2 << 22)
# define SDIDCON_IRQPERIOD (1 << 21)
# define SDIDCON_TXAFTERRESP (1 << 20)
# define SDIDCON_RXAFTERCMD (1 << 19)
# define SDIDCON_BUSYAFTERCMD (1 << 18)
# define SDIDCON_BLOCKMODE (1 << 17)
# define SDIDCON_WIDEBUS (1 << 16)
# define SDIDCON_DMAEN (1 << 15)
# define SDIDCON_STOP (0 << 14)
# define SDIDCON_DATSTART (1 << 14)
# define SDIDCON_DATMODE (3 << 12)
# define SDIDCON_BLKNUM (0xfff)
# define SDIDCON_XFER_READY    (0 << 12)
# define SDIDCON_XFER_CHKSTART (1 << 12)
# define SDIDCON_XFER_RXSTART  (2 << 12)
# define SDIDCON_XFER_TXSTART  (3 << 12)

#define SDIDCNT 0x30
# define SDIDCNT_BLKNUM_SHIFT 12

#define SDIDSTA 0x34
# define SDIDSTA_RDYWAITREQ (1 << 10)
# define SDIDSTA_SDIOIRQDETECT (1 << 9)
# define SDIDSTA_FIFOFAIL (1 << 8) /* reserved on 2440 */
# define SDIDSTA_CRCFAIL (1 << 7)
# define SDIDSTA_RXCRCFAIL (1 << 6)
# define SDIDSTA_DATATIMEOUT (1 << 5)
# define SDIDSTA_XFERFINISH (1 << 4)
# define SDIDSTA_BUSYFINISH (1 << 3)
# define SDIDSTA_SBITERR (1 << 2) /* reserved on 2410a/2440 */
# define SDIDSTA_TXDATAON (1 << 1)
# define SDIDSTA_RXDATAON (1 << 0)

#define SDIFSTA 0x38
# define SDIFSTA_FIFORESET (1<<16)
# define SDIFSTA_FIFOFAIL (3<<14)  /* 3 is correct (2 bits) */
# define SDIFSTA_TFDET (1<<13)
# define SDIFSTA_RFDET (1<<12)
# define SDIFSTA_TFHALF (1<<11)
# define SDIFSTA_TFEMPTY (1<<10)
# define SDIFSTA_RFLAST (1<<9)
# define SDIFSTA_RFFULL (1<<8)
# define SDIFSTA_RFHALF (1<<7)
# define SDIFSTA_COUNTMASK (0x7f)

#define SDIIMSK 0x3C
# define SDIIMSK_RESPONSECRC    (1<<17)
# define SDIIMSK_CMDSENT        (1<<16)
# define SDIIMSK_CMDTIMEOUT     (1<<15)
# define SDIIMSK_RESPONSEND     (1<<14)
# define SDIIMSK_READWAIT       (1<<13)
# define SDIIMSK_SDIOIRQ        (1<<12)
# define SDIIMSK_FIFOFAIL       (1<<11)
# define SDIIMSK_CRCSTATUS      (1<<10)
# define SDIIMSK_DATACRC        (1<<9)
# define SDIIMSK_DATATIMEOUT    (1<<8)
# define SDIIMSK_DATAFINISH     (1<<7)
# define SDIIMSK_BUSYFINISH     (1<<6)
# define SDIIMSK_SBITERR        (1<<5) /* reserved 2440/2410a */
# define SDIIMSK_TXFIFOHALF     (1<<4)
# define SDIIMSK_TXFIFOEMPTY    (1<<3)
# define SDIIMSK_RXFIFOLAST     (1<<2)
# define SDIIMSK_RXFIFOFULL     (1<<1)
# define SDIIMSK_RXFIFOHALF     (1<<0)

#define SDIDATA 0x40

struct s3c_mci_host {
	struct mci_host	host;
	void __iomem	*base;
	int		bus_width:2; /* 0 = 1 bit, 1 = 4 bit, 2 = 8 bit */
	unsigned	clock;	/* current clock in Hz */
	unsigned	data_size;	/* data transfer in bytes */
};

#define to_s3c_host(h)	container_of(h, struct s3c_mci_host, host)

/**
 * Finish a request
 * @param hw_dev Host interface instance
 *
 * Just a little bit paranoia.
 */
static void s3c_finish_request(struct s3c_mci_host *host_data)
{
	/* TODO ensure the engines are stopped */
}

/**
 * Setup a new clock frequency on this MCI bus
 * @param hw_dev Host interface instance
 * @param nc New clock value in Hz (can be 0)
 * @return New clock value (may differ from 'nc')
 */
static unsigned s3c_setup_clock_speed(struct s3c_mci_host *host_data, unsigned nc)
{
	unsigned clock;
	uint32_t mci_psc;

	if (nc == 0)
		return 0;

	clock = s3c_get_pclk();
	/* Calculate the required prescaler value to get the requested frequency */
	mci_psc = (clock + (nc >> 2)) / nc;

	if (mci_psc > 256) {
		mci_psc = 256;
		pr_warning("SD/MMC clock might be too high!\n");
	}

	writel(mci_psc - 1, host_data->base + SDIPRE);

	return clock / mci_psc;
}

/**
 * Reset the MCI engine (the hard way)
 * @param hw_dev Host interface instance
 *
 * This will reset everything in all registers of this unit!
 */
static void s3c_mci_reset(struct s3c_mci_host *host_data)
{
	/* reset the hardware */
	writel(SDICON_SDRESET, host_data->base + SDICON);
	/* wait until reset it finished */
	while (readl(host_data->base + SDICON) & SDICON_SDRESET)
		;
}

/**
 * Initialize hard and software
 * @param hw_dev Host interface instance
 * @param mci_dev MCI device instance (might be NULL)
 */
static int s3c_mci_initialize(struct s3c_mci_host *host_data, struct device_d *mci_dev)
{
	s3c_mci_reset(host_data);

	/* restore last settings */
	host_data->clock = s3c_setup_clock_speed(host_data, host_data->clock);
	writel(0x007FFFFF, host_data->base + SDITIMER);
	writel(SDICON_MMCCLOCK, host_data->base + SDICON);
	writel(512, host_data->base + SDIBSIZE);

	return 0;
}

/**
 * Prepare engine's bits for the next command transfer
 * @param cmd_flags MCI's command flags
 * @param data_flags MCI's data flags
 * @return Register bits for this transfer
 */
static uint32_t s3c_prepare_command_setup(unsigned cmd_flags, unsigned data_flags)
{
	uint32_t reg;

	/* source (=host) */
	reg = SDICMDCON_SENDERHOST;

	if (cmd_flags & MMC_RSP_PRESENT) {
		reg |= SDICMDCON_WAITRSP;
		pr_debug("Command with response\n");
	}
	if (cmd_flags & MMC_RSP_136) {
		reg |= SDICMDCON_LONGRSP;
		pr_debug("Command with long response\n");
	}
	if (cmd_flags & MMC_RSP_CRC)
		; /* FIXME */
	if (cmd_flags & MMC_RSP_BUSY)
		; /* FIXME */
	if (cmd_flags & MMC_RSP_OPCODE)
		; /* FIXME */
	if (data_flags != 0)
		reg |= SDICMDCON_WITHDATA;

	return reg;
}

/**
 * Prepare engine's bits for the next data transfer
 * @param hw_dev Host interface device instance
 * @param data_flags MCI's data flags
 * @return Register bits for this transfer
 */
static uint32_t s3c_prepare_data_setup(struct s3c_mci_host *host_data, unsigned data_flags)
{
	uint32_t reg = SDIDCON_BLOCKMODE;	/* block mode only is supported */

	if (host_data->bus_width == 1)
		reg |= SDIDCON_WIDEBUS;

	/* enable any kind of data transfers on demand only */
	if (data_flags & MMC_DATA_WRITE)
		reg |= SDIDCON_TXAFTERRESP | SDIDCON_XFER_TXSTART;

	if (data_flags & MMC_DATA_READ)
		reg |= SDIDCON_RXAFTERCMD | SDIDCON_XFER_RXSTART;

	/* TODO: Support more than the 2440 CPU */
	reg |= SDIDCON_DS_WORD | SDIDCON_DATSTART;

	return reg;
}

/**
 * Terminate a current running transfer
 * @param hw_dev Host interface device instance
 * @return 0 on success
 *
 * Note: Try to stop a running transfer. This should not happen, as all
 * transfers must complete in this driver. But who knows... ;-)
 */
static int s3c_terminate_transfer(struct s3c_mci_host *host_data)
{
	unsigned stoptries = 3;

	while (readl(host_data->base + SDIDSTA) & (SDIDSTA_TXDATAON | SDIDSTA_RXDATAON)) {
		pr_debug("Transfer still in progress.\n");

		writel(SDIDCON_STOP, host_data->base + SDIDCON);
		s3c_mci_initialize(host_data, NULL);

		if ((stoptries--) == 0) {
			pr_warning("Cannot stop the engine!\n");
			return -EINVAL;
		}
	}

	return 0;
}

/**
 * Setup registers for data transfer
 * @param hw_dev Host interface device instance
 * @param data The data information (buffer, direction aso.)
 * @return 0 on success
 */
static int s3c_prepare_data_transfer(struct s3c_mci_host *host_data, struct mci_data *data)
{
	uint32_t reg;

	writel(data->blocksize, host_data->base + SDIBSIZE);
	reg = s3c_prepare_data_setup(host_data, data->flags);
	reg |= data->blocks & SDIDCON_BLKNUM;
	writel(reg, host_data->base + SDIDCON);
	writel(0x007FFFFF, host_data->base + SDITIMER);

	return 0;
}

/**
 * Send a command and receive the response
 * @param hw_dev Host interface device instance
 * @param cmd The command to handle
 * @param data The data information (buffer, direction aso.)
 * @return 0 on success
 */
static int s3c_send_command(struct s3c_mci_host *host_data, struct mci_cmd *cmd,
				struct mci_data *data)
{
	uint32_t reg, t1;
	int rc;

	writel(0x007FFFFF, host_data->base + SDITIMER);

	/* setup argument */
	writel(cmd->cmdarg, host_data->base + SDICMDARG);

	/* setup command and transfer characteristic */
	reg = s3c_prepare_command_setup(cmd->resp_type, data != NULL ? data->flags : 0);
	reg |= cmd->cmdidx & SDICMDCON_INDEX;

	/* run the command right now */
	writel(reg | SDICMDCON_CMDSTART, host_data->base + SDICMDCON);
	t1 = readl(host_data->base + SDICMDSTAT);
	/* wait until command is done */
	while (1) {
		reg = readl(host_data->base + SDICMDSTAT);
		/* done? */
		if (cmd->resp_type & MMC_RSP_PRESENT) {
			if (reg & SDICMDSTAT_RSPFIN) {
				writel(SDICMDSTAT_RSPFIN,
					host_data->base + SDICMDSTAT);
				rc = 0;
				break;
			}
		} else {
			if (reg & SDICMDSTAT_CMDSENT) {
					writel(SDICMDSTAT_CMDSENT,
						host_data->base + SDICMDSTAT);
					rc = 0;
					break;
			}
		}
		/* timeout? */
		if (reg & SDICMDSTAT_CMDTIMEOUT) {
			writel(SDICMDSTAT_CMDTIMEOUT,
				host_data->base + SDICMDSTAT);
			rc = -ETIMEDOUT;
			break;
		}
	}

	if ((rc == 0) && (cmd->resp_type & MMC_RSP_PRESENT)) {
		cmd->response[0] = readl(host_data->base + SDIRSP0);
		cmd->response[1] = readl(host_data->base + SDIRSP1);
		cmd->response[2] = readl(host_data->base + SDIRSP2);
		cmd->response[3] = readl(host_data->base + SDIRSP3);
	}
	/* do not disable the clock! */
	return rc;
}

/**
 * Clear major registers prior a new transaction
 * @param hw_dev Host interface device instance
 * @return 0 on success
 *
 * FIFO clear is only necessary on 2440, but doesn't hurt on 2410
 */
static int s3c_prepare_engine(struct s3c_mci_host *host_data)
{
	int rc;

	rc = s3c_terminate_transfer(host_data);
	if (rc != 0)
		return rc;

	writel(-1, host_data->base + SDICMDSTAT);
	writel(-1, host_data->base + SDIDSTA);
	writel(-1, host_data->base + SDIFSTA);

	return 0;
}

/**
 * Handle MCI commands without data
 * @param hw_dev Host interface device instance
 * @param cmd The command to handle
 * @return 0 on success
 *
 * This functions handles the following MCI commands:
 * - "broadcast command (BC)" without a response
 * - "broadcast commands with response (BCR)"
 * - "addressed command (AC)" with response, but without data
 */
static int s3c_mci_std_cmds(struct s3c_mci_host *host_data, struct mci_cmd *cmd)
{
	int rc;

	rc = s3c_prepare_engine(host_data);
	if (rc != 0)
		return 0;

	return s3c_send_command(host_data, cmd, NULL);
}

/**
 * Read one block of data from the FIFO
 * @param hw_dev Host interface device instance
 * @param data The data information (buffer, direction aso.)
 * @return 0 on success
 */
static int s3c_mci_read_block(struct s3c_mci_host *host_data, struct mci_data *data)
{
	uint32_t *p;
	unsigned cnt, data_size;

#define READ_REASON_TO_FAIL (SDIDSTA_CRCFAIL | SDIDSTA_RXCRCFAIL | SDIDSTA_DATATIMEOUT)

	p = (uint32_t*)data->dest;
	data_size = data->blocksize * data->blocks;

	while (data_size > 0) {

		/* serious error? */
		if (readl(host_data->base + SDIDSTA) & READ_REASON_TO_FAIL) {
			pr_err("Failed while reading data\n");
			return -EIO;
		}

		/* now check the FIFO status */
		if (readl(host_data->base + SDIFSTA) & SDIFSTA_FIFOFAIL) {
			pr_err("Data loss due to FIFO overflow when reading\n");
			return -EIO;
		}

		/* we only want to read full words */
		cnt = (readl(host_data->base + SDIFSTA) & SDIFSTA_COUNTMASK) >> 2;

		/* read one chunk of data from the FIFO */
		while (cnt--) {
			*p = readl(host_data->base + SDIDATA);
			p++;
			if (data_size >= 4)
				data_size -= 4;
			else {
				data_size = 0;
				break;
			}
		}
	}

	return 0;
}

/**
 * Write one block of data into the FIFO
 * @param hw_dev Host interface device instance
 * @param cmd The command to handle
 * @param data The data information (buffer, direction aso.)
 * @return 0 on success
 *
 * We must ensure data in the FIFO when the command phase changes into the
 * data phase. To ensure this, the FIFO gets filled first, then the command.
 */
static int s3c_mci_write_block(struct s3c_mci_host *host_data, struct mci_cmd *cmd,
				struct mci_data *data)
{
	const uint32_t *p = (const uint32_t*)data->src;
	unsigned cnt, data_size;
	uint32_t reg;

#define WRITE_REASON_TO_FAIL (SDIDSTA_CRCFAIL | SDIDSTA_DATATIMEOUT)

	data_size = data->blocksize * data->blocks;
	/*
	 * With high clock rates we must fill the FIFO as early as possible
	 * Its size is 16 words. We assume its empty, when this function is
	 * entered.
	 */
	cnt = 16;
	while (cnt--) {
		writel(*p, host_data->base + SDIDATA);
		p++;
		if (data_size >= 4)
			data_size -= 4;
		else {
			data_size = 0;
			break;
		}
	}

	/* data is now in place and waits for transmitt. Start the command right now */
	s3c_send_command(host_data, cmd, data);

	if ((reg = readl(host_data->base + SDIFSTA)) & SDIFSTA_FIFOFAIL) {
		pr_err("Command fails immediatly due to FIFO underrun when writing %08X\n",
			reg);
		return -EIO;
	}

	while (data_size > 0) {

		if (readl(host_data->base + SDIDSTA) & WRITE_REASON_TO_FAIL) {
			pr_err("Failed writing data\n");
			return -EIO;
		}

		/* now check the FIFO status */
		if ((reg = readl(host_data->base + SDIFSTA)) & SDIFSTA_FIFOFAIL) {
			pr_err("Data loss due to FIFO underrun when writing %08X\n",
					reg);
			return -EIO;
		}

		/* we only want to write full words */
		cnt = 16 - (((readl(host_data->base + SDIFSTA) & SDIFSTA_COUNTMASK) + 3) >> 2);

		/* fill the FIFO if it has free entries */
		while (cnt--) {
			writel(*p, host_data->base + SDIDATA);
			p++;
			if (data_size >= 4)
				data_size -= 4;
			else {
				data_size = 0;
				break;
			}
		}
	}

	return 0;
}

/**
 * Handle MCI commands with or without data
 * @param hw_dev Host interface device instance
 * @param cmd The command to handle
 * @param data The data information (buffer, direction aso.)
 * @return 0 on success
*/
static int s3c_mci_adtc(struct s3c_mci_host *host_data, struct mci_cmd *cmd,
			struct mci_data *data)
{
	int rc;

	rc = s3c_prepare_engine(host_data);
	if (rc != 0)
		return rc;

	rc = s3c_prepare_data_transfer(host_data, data);
	if (rc != 0)
		return rc;

	if (data->flags & MMC_DATA_READ) {
		s3c_send_command(host_data, cmd, data);
		rc = s3c_mci_read_block(host_data, data);
		if (rc == 0) {
			while (!(readl(host_data->base + SDIDSTA) & SDIDSTA_XFERFINISH))
				;
		} else
			s3c_terminate_transfer(host_data);
	}

	if (data->flags & MMC_DATA_WRITE) {
		rc = s3c_mci_write_block(host_data, cmd, data);
		if (rc == 0) {
			while (!(readl(host_data->base + SDIDSTA) & SDIDSTA_XFERFINISH))
				;
		} else
			s3c_terminate_transfer(host_data);
	}
	writel(0, host_data->base + SDIDCON);

	return rc;
}

/* ------------------------- MCI API -------------------------------------- */

/**
 * Keep the attached MMC/SD unit in a well know state
 * @param host MCI host
 * @param mci_dev MCI device instance
 * @return 0 on success, negative value else
 */
static int mci_reset(struct mci_host *host, struct device_d *mci_dev)
{
	struct s3c_mci_host *host_data = to_s3c_host(host);

	return s3c_mci_initialize(host_data, mci_dev);
}

/**
 * Process one command to the MCI card
 * @param host MCI host
 * @param cmd The command to process
 * @param data The data to handle in the command (can be NULL)
 * @return 0 on success, negative value else
 */
static int mci_request(struct mci_host *host, struct mci_cmd *cmd,
			struct mci_data *data)
{
	struct s3c_mci_host *host_data = to_s3c_host(host);
	int rc;

	/* enable clock */
	writel(readl(host_data->base + SDICON) | SDICON_CLKEN,
		host_data->base + SDICON);

	if ((cmd->resp_type == 0) || (data == NULL))
		rc = s3c_mci_std_cmds(host_data, cmd);
	else
		rc = s3c_mci_adtc(host_data, cmd, data);	/* with response and data */

	s3c_finish_request(host_data);

	/* disable clock */
	writel(readl(host_data->base + SDICON) & ~SDICON_CLKEN,
		host_data->base + SDICON);
	return rc;
}

/**
 * Setup the bus width and IO speed
 * @param host MCI host
 * @param bus_width New bus width value (1, 4 or 8)
 * @param clock New clock in Hz (can be '0' to disable the clock)
 */
static void mci_set_ios(struct mci_host *host, struct mci_ios *ios)
{
	struct s3c_mci_host *host_data = to_s3c_host(host);
	uint32_t reg;

	switch (ios->bus_width) {
	case MMC_BUS_WIDTH_4:
		host_data->bus_width = 1;
		break;
	case MMC_BUS_WIDTH_1:
		host_data->bus_width = 0;
		break;
	default:
		return;
	}

	reg = readl(host_data->base + SDICON);
	if (ios->clock) {
		/* setup the IO clock frequency and enable it */
		host_data->clock = s3c_setup_clock_speed(host_data, ios->clock);
		reg |= SDICON_CLKEN;	/* enable the clock */
	} else {
		reg &= ~SDICON_CLKEN;	/* disable the clock */
		host_data->clock = 0;
	}
	writel(reg, host_data->base + SDICON);

	pr_debug("IO settings: bus width=%d, frequency=%u Hz\n",
		host_data->bus_width, host_data->clock);
}

/* ----------------------------------------------------------------------- */

static void s3c_info(struct device_d *hw_dev)
{
	struct s3c_mci_host *host = hw_dev->priv;
	struct s3c_mci_platform_data *pd = hw_dev->platform_data;

	printf("  Bus data width: %d bit\n", host->bus_width == 1 ? 4 : 1);
	printf("  Bus frequency: %u Hz\n", host->clock);
	printf("   Frequency limits: ");
	if (pd->f_min == 0)
		printf("no lower limit ");
	else
		printf("%u Hz lower limit ", pd->f_min);
	if (pd->f_max == 0)
		printf("- no upper limit");
	else
		printf("- %u Hz upper limit", pd->f_max);
	printf("\n  Card detection support: %s\n",
		pd->gpio_detect != 0 ? "yes" : "no");
}

static int s3c_mci_probe(struct device_d *hw_dev)
{
	struct s3c_mci_host *s3c_host;
	struct s3c_mci_platform_data *pd = hw_dev->platform_data;

	s3c_host = xzalloc(sizeof(*s3c_host));
	s3c_host->host.send_cmd = mci_request;
	s3c_host->host.set_ios = mci_set_ios;
	s3c_host->host.init = mci_reset;

	/* TODO replace by the global func: enable the SDI unit clock */
	writel(readl(S3C_CLOCK_POWER_BASE + 0x0c) | 0x200,
		S3C_CLOCK_POWER_BASE + 0x0c);

	if (pd == NULL) {
		pr_err("Missing platform data\n");
		return -EINVAL;
	}

	hw_dev->priv = s3c_host;
	s3c_host->base = dev_request_mem_region(hw_dev, 0);
	s3c_host->host.hw_dev = hw_dev;

	/* feed forward the platform specific values */
	s3c_host->host.voltages = pd->voltages;
	s3c_host->host.host_caps = pd->caps;
	s3c_host->host.f_min = pd->f_min == 0 ? s3c_get_pclk() / 256 : pd->f_min;
	s3c_host->host.f_max = pd->f_max == 0 ? s3c_get_pclk() / 2 : pd->f_max;

	if (IS_ENABLED(iCONFIG_MCI_INFO))
		hw_dev->info = s3c_info;

	/*
	 * Start the clock to let the engine and the card finishes its startup
	 */
	s3c_host->clock = s3c_setup_clock_speed(s3c_host, pd->f_min);
	writel(SDICON_FIFORESET | SDICON_MMCCLOCK, s3c_host->base + SDICON);

	return mci_register(&s3c_host->host);
}

static struct driver_d s3c_mci_driver = {
        .name  = "s3c_mci",
        .probe = s3c_mci_probe,
};
device_platform_driver(s3c_mci_driver);