summaryrefslogtreecommitdiffstats
path: root/drivers/net/liteeth.c
blob: a952a1d924a70765960859f3c36f6148cb8d2ccd (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
// SPDX-License-Identifier: GPL-2.0
/*
 * LiteX Liteeth Ethernet
 *
 * Copyright 2017 Joel Stanley <joel@jms.id.au>
 *
 * Ported to barebox from linux kernel
 *   Copyright (C) 2019-2021 Antony Pavlov <antonynpavlov@gmail.com>
 *   Copyright (C) 2021 Marek Czerski <m.czerski@ap-tech.pl>
 *
 */

#include <common.h>
#include <io.h>
#include <linux/iopoll.h>
#include <malloc.h>
#include <net.h>
#include <init.h>
#include <of_net.h>
#include <linux/phy.h>
#include <linux/mdio-bitbang.h>

#define DRV_NAME	"liteeth"

#define LITEETH_WRITER_SLOT		0x00
#define LITEETH_WRITER_LENGTH		0x04
#define LITEETH_WRITER_ERRORS		0x08
#define LITEETH_WRITER_EV_STATUS	0x0c
#define LITEETH_WRITER_EV_PENDING	0x10
#define LITEETH_WRITER_EV_ENABLE	0x14
#define LITEETH_READER_START		0x18
#define LITEETH_READER_READY		0x1c
#define LITEETH_READER_LEVEL		0x20
#define LITEETH_READER_SLOT		0x24
#define LITEETH_READER_LENGTH		0x28
#define LITEETH_READER_EV_STATUS	0x2c
#define LITEETH_READER_EV_PENDING	0x30
#define LITEETH_READER_EV_ENABLE	0x34
#define LITEETH_PREAMBLE_CRC		0x38
#define LITEETH_PREAMBLE_ERRORS		0x3c
#define LITEETH_CRC_ERRORS		0x40

#define LITEETH_PHY_CRG_RESET		0x00
#define LITEETH_MDIO_W			0x04
#define  MDIO_W_CLK			BIT(0)
#define  MDIO_W_OE			BIT(1)
#define  MDIO_W_DO			BIT(2)

#define LITEETH_MDIO_R			0x08
#define  MDIO_R_DI			BIT(0)

#define LITEETH_BUFFER_SIZE		0x800
#define MAX_PKT_SIZE			LITEETH_BUFFER_SIZE

struct liteeth {
	struct device_d *dev;
	struct eth_device edev;
	void __iomem *base;
	void __iomem *mdio_base;
	struct mii_bus *mii_bus;
	struct mdiobb_ctrl mdiobb;

	/* Link management */
	int cur_duplex;
	int cur_speed;

	/* Tx */
	int tx_slot;
	int num_tx_slots;
	void __iomem *tx_base;

	/* Rx */
	int rx_slot;
	int num_rx_slots;
	void __iomem *rx_base;
};

static inline void litex_write8(void __iomem *addr, u8 val)
{
	writeb(val, addr);
}

static inline void litex_write16(void __iomem *addr, u16 val)
{
	writew(val, addr);
}

static inline u8 litex_read8(void __iomem *addr)
{
	return readb(addr);
}

static inline u32 litex_read32(void __iomem *addr)
{
	return readl(addr);
}

static void liteeth_mdio_w_modify(struct liteeth *priv, u8 clear, u8 set)
{
	void __iomem *mdio_w = priv->mdio_base + LITEETH_MDIO_W;

	litex_write8(mdio_w, (litex_read8(mdio_w) & ~clear) | set);
}

static void liteeth_mdio_ctrl(struct mdiobb_ctrl *ctrl, u8 mask, int set)
{
	struct liteeth *priv = container_of(ctrl, struct liteeth, mdiobb);

	liteeth_mdio_w_modify(priv, mask, set ? mask : 0);
}

/* MDC pin control */
static void liteeth_set_mdc(struct mdiobb_ctrl *ctrl, int level)
{
	liteeth_mdio_ctrl(ctrl, MDIO_W_CLK, level);
}

/* Data I/O pin control */
static void liteeth_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output)
{
	liteeth_mdio_ctrl(ctrl, MDIO_W_OE, output);
}

/* Set data bit */
static void liteeth_set_mdio_data(struct mdiobb_ctrl *ctrl, int value)
{
	liteeth_mdio_ctrl(ctrl, MDIO_W_DO, value);
}

/* Get data bit */
static int liteeth_get_mdio_data(struct mdiobb_ctrl *ctrl)
{
	struct liteeth *priv = container_of(ctrl, struct liteeth, mdiobb);

	return (litex_read8(priv->mdio_base + LITEETH_MDIO_R) & MDIO_R_DI) != 0;
}

/* MDIO bus control struct */
static struct mdiobb_ops bb_ops = {
	.set_mdc = liteeth_set_mdc,
	.set_mdio_dir = liteeth_set_mdio_dir,
	.set_mdio_data = liteeth_set_mdio_data,
	.get_mdio_data = liteeth_get_mdio_data,
};

static int liteeth_init_dev(struct eth_device *edev)
{
	return 0;
}

static int liteeth_eth_open(struct eth_device *edev)
{
	struct liteeth *priv = edev->priv;
	int ret;

	/* Disable events */
	litex_write8(priv->base + LITEETH_WRITER_EV_ENABLE, 0);
	litex_write8(priv->base + LITEETH_READER_EV_ENABLE, 0);

	/* Clear pending events? */
	litex_write8(priv->base + LITEETH_WRITER_EV_PENDING, 1);
	litex_write8(priv->base + LITEETH_READER_EV_PENDING, 1);

	ret = phy_device_connect(edev, priv->mii_bus, -1, NULL, 0, -1);
	if (ret)
		return ret;

	return 0;
}

static int liteeth_eth_send(struct eth_device *edev, void *packet,
				int packet_length)
{
	struct liteeth *priv = edev->priv;
	void *txbuffer;
	int ret;
	u8 val;
	u8 reg;

	reg = litex_read8(priv->base + LITEETH_READER_EV_PENDING);
	if (reg) {
		litex_write8(priv->base + LITEETH_READER_EV_PENDING, reg);
	}

	/* Reject oversize packets */
	if (unlikely(packet_length > MAX_PKT_SIZE)) {
		dev_err(priv->dev, "tx packet too big\n");
		goto drop;
	}

	txbuffer = priv->tx_base + priv->tx_slot * LITEETH_BUFFER_SIZE;
	memcpy(txbuffer, packet, packet_length);
	litex_write8(priv->base + LITEETH_READER_SLOT, priv->tx_slot);
	litex_write16(priv->base + LITEETH_READER_LENGTH, packet_length);

	ret = readb_poll_timeout(priv->base + LITEETH_READER_READY,
			val, val, 1000);
	if (ret == -ETIMEDOUT) {
		dev_err(priv->dev, "LITEETH_READER_READY timed out\n");
		goto drop;
	}

	litex_write8(priv->base + LITEETH_READER_START, 1);

	priv->tx_slot = (priv->tx_slot + 1) % priv->num_tx_slots;

drop:
	return 0;
}

static int liteeth_eth_rx(struct eth_device *edev)
{
	struct liteeth *priv = edev->priv;
	u8 rx_slot;
	int len = 0;
	u8 reg;

	reg = litex_read8(priv->base + LITEETH_WRITER_EV_PENDING);
	if (!reg) {
		goto done;
	}

	len = litex_read32(priv->base + LITEETH_WRITER_LENGTH);
	if (len == 0 || len > 2048) {
		len = 0;
		dev_err(priv->dev, "%s: invalid len %d\n", __func__, len);
		litex_write8(priv->base + LITEETH_WRITER_EV_PENDING, reg);
		goto done;
	}

	rx_slot = litex_read8(priv->base + LITEETH_WRITER_SLOT);

	memcpy(NetRxPackets[0], priv->rx_base + rx_slot * LITEETH_BUFFER_SIZE, len);

	net_receive(edev, NetRxPackets[0], len);

	litex_write8(priv->base + LITEETH_WRITER_EV_PENDING, reg);

done:
	return len;
}

static void liteeth_eth_halt(struct eth_device *edev)
{
	struct liteeth *priv = edev->priv;

	litex_write8(priv->base + LITEETH_WRITER_EV_ENABLE, 0);
	litex_write8(priv->base + LITEETH_READER_EV_ENABLE, 0);
}

static void liteeth_reset_hw(struct liteeth *priv)
{
	/* Reset, twice */
	litex_write8(priv->base + LITEETH_PHY_CRG_RESET, 0);
	udelay(10);
	litex_write8(priv->base + LITEETH_PHY_CRG_RESET, 1);
	udelay(10);
	litex_write8(priv->base + LITEETH_PHY_CRG_RESET, 0);
	udelay(10);
}

static int liteeth_get_ethaddr(struct eth_device *edev, unsigned char *m)
{
	return 0;
}

static int liteeth_set_ethaddr(struct eth_device *edev,
					const unsigned char *mac_addr)
{
	return 0;
}

static int liteeth_probe(struct device_d *dev)
{
	struct device_node *np = dev->device_node;
	struct eth_device *edev;
	void __iomem *buf_base;
	struct liteeth *priv;
	int err;

	priv = xzalloc(sizeof(struct liteeth));
	edev = &priv->edev;
	edev->priv = priv;
	priv->dev = dev;

	priv->base = dev_request_mem_region(dev, 0);
	if (IS_ERR(priv->base)) {
		err = PTR_ERR(priv->base);
		goto err;
	}

	priv->mdio_base = dev_request_mem_region(dev, 1);
	if (IS_ERR(priv->mdio_base)) {
		err = PTR_ERR(priv->mdio_base);
		goto err;
	}

	buf_base = dev_request_mem_region(dev, 2);
	if (IS_ERR(buf_base)) {
		err = PTR_ERR(buf_base);
		goto err;
	}

	err = of_property_read_u32(np, "rx-fifo-depth",
			&priv->num_rx_slots);
	if (err) {
		dev_err(dev, "unable to get rx-fifo-depth\n");
		goto err;
	}

	err = of_property_read_u32(np, "tx-fifo-depth",
			&priv->num_tx_slots);
	if (err) {
		dev_err(dev, "unable to get tx-fifo-depth\n");
		goto err;
	}

	/* Rx slots */
	priv->rx_base = buf_base;
	priv->rx_slot = 0;

	/* Tx slots come after Rx slots */
	priv->tx_base = buf_base + priv->num_rx_slots * LITEETH_BUFFER_SIZE;
	priv->tx_slot = 0;

	edev->init = liteeth_init_dev;
	edev->open = liteeth_eth_open;
	edev->send = liteeth_eth_send;
	edev->recv = liteeth_eth_rx;
	edev->get_ethaddr = liteeth_get_ethaddr;
	edev->set_ethaddr = liteeth_set_ethaddr;
	edev->halt = liteeth_eth_halt;
	edev->parent = dev;

	priv->mdiobb.ops = &bb_ops;

	priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb);
	priv->mii_bus->parent = dev;

	liteeth_reset_hw(priv);

	err = eth_register(edev);
	if (err) {
		dev_err(dev, "failed to register edev\n");
		goto err;
	}

	err = mdiobus_register(priv->mii_bus);
	if (err) {
		dev_err(dev, "failed to register mii_bus\n");
		goto err;
	}

	dev_info(dev, DRV_NAME " driver registered\n");

	return 0;

err:
	return err;
}

static const struct of_device_id liteeth_dt_ids[] = {
	{
		.compatible = "litex,liteeth"
	}, {
	}
};

static struct driver_d liteeth_driver = {
	.name = DRV_NAME,
	.probe = liteeth_probe,
	.of_compatible = DRV_OF_COMPAT(liteeth_dt_ids),
};
device_platform_driver(liteeth_driver);

MODULE_AUTHOR("Joel Stanley <joel@jms.id.au>");
MODULE_LICENSE("GPL");