summaryrefslogtreecommitdiffstats
path: root/dts/Bindings/arm/bcm/brcm,brcmstb.txt
blob: c052caad36e806907988fa20e8250f2dce7d90d6 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
ARM Broadcom STB platforms Device Tree Bindings
-----------------------------------------------
Boards with Broadcom Brahma15 ARM-based BCMxxxx (generally BCM7xxx variants)
SoC shall have the following DT organization:

Required root node properties:
    - compatible: "brcm,bcm<chip_id>", "brcm,brcmstb"

example:
/ {
    #address-cells = <2>;
    #size-cells = <2>;
    model = "Broadcom STB (bcm7445)";
    compatible = "brcm,bcm7445", "brcm,brcmstb";

Further, syscon nodes that map platform-specific registers used for general
system control is required:

    - compatible: "brcm,bcm<chip_id>-sun-top-ctrl", "syscon"
    - compatible: "brcm,bcm<chip_id>-cpu-biu-ctrl",
		  "brcm,brcmstb-cpu-biu-ctrl",
		  "syscon"
    - compatible: "brcm,bcm<chip_id>-hif-continuation", "syscon"

cpu-biu-ctrl node
-------------------
SoCs with Broadcom Brahma15 ARM-based and Brahma53 ARM64-based CPUs have a
specific Bus Interface Unit (BIU) block which controls and interfaces the CPU
complex to the different Memory Controller Ports (MCP), one per memory
controller (MEMC). This BIU block offers a feature called Write Pairing which
consists in collapsing two adjacent cache lines into a single (bursted) write
transaction towards the memory controller (MEMC) to maximize write bandwidth.

Required properties:

    - compatible: must be "brcm,bcm7445-cpu-biu-ctrl", "brcm,brcmstb-cpu-biu-ctrl", "syscon"

Optional properties:

    - brcm,write-pairing:
	Boolean property, which when present indicates that the chip
	supports write-pairing.

example:
    rdb {
        #address-cells = <1>;
        #size-cells = <1>;
        compatible = "simple-bus";
        ranges = <0 0x00 0xf0000000 0x1000000>;

        sun_top_ctrl: syscon@404000 {
            compatible = "brcm,bcm7445-sun-top-ctrl", "syscon";
            reg = <0x404000 0x51c>;
        };

        hif_cpubiuctrl: syscon@3e2400 {
            compatible = "brcm,bcm7445-cpu-biu-ctrl", "brcm,brcmstb-cpu-biu-ctrl", "syscon";
            reg = <0x3e2400 0x5b4>;
            brcm,write-pairing;
        };

        hif_continuation: syscon@452000 {
            compatible = "brcm,bcm7445-hif-continuation", "syscon";
            reg = <0x452000 0x100>;
        };
    };

Nodes that allow for support of SMP initialization and reboot are required:

smpboot
-------
Required properties:

    - compatible
        The string "brcm,brcmstb-smpboot".

    - syscon-cpu
        A phandle / integer array property which lets the BSP know the location
        of certain CPU power-on registers.

        The layout of the property is as follows:
            o a phandle to the "hif_cpubiuctrl" syscon node
            o offset to the base CPU power zone register
            o offset to the base CPU reset register

    - syscon-cont
        A phandle pointing to the syscon node which describes the CPU boot
        continuation registers.
            o a phandle to the "hif_continuation" syscon node

example:
    smpboot {
        compatible = "brcm,brcmstb-smpboot";
        syscon-cpu = <&hif_cpubiuctrl 0x88 0x178>;
        syscon-cont = <&hif_continuation>;
    };

reboot
-------
Required properties

    - compatible
        The string property "brcm,brcmstb-reboot" for 40nm/28nm chips with
        the new SYS_CTRL interface, or "brcm,bcm7038-reboot" for 65nm
        chips with the old SUN_TOP_CTRL interface.

    - syscon
        A phandle / integer array that points to the syscon node which describes
        the general system reset registers.
            o a phandle to "sun_top_ctrl"
            o offset to the "reset source enable" register
            o offset to the "software master reset" register

example:
    reboot {
        compatible = "brcm,brcmstb-reboot";
        syscon = <&sun_top_ctrl 0x304 0x308>;
    };



Power management
----------------

For power management (particularly, S2/S3/S5 system suspend), the following SoC
components are needed:

= Always-On control block (AON CTRL)

This hardware provides control registers for the "always-on" (even in low-power
modes) hardware, such as the Power Management State Machine (PMSM).

Required properties:
- compatible     : should contain "brcm,brcmstb-aon-ctrl"
- reg            : the register start and length for the AON CTRL block

Example:

aon-ctrl@410000 {
	compatible = "brcm,brcmstb-aon-ctrl";
	reg = <0x410000 0x400>;
};

= Memory controllers

A Broadcom STB SoC typically has a number of independent memory controllers,
each of which may have several associated hardware blocks, which are versioned
independently (control registers, DDR PHYs, etc.). One might consider
describing these controllers as a parent "memory controllers" block, which
contains N sub-nodes (one for each controller in the system), each of which is
associated with a number of hardware register resources (e.g., its PHY). See
the example device tree snippet below.

== MEMC (MEMory Controller)

Represents a single memory controller instance.

Required properties:
- compatible     : should contain "brcm,brcmstb-memc" and "simple-bus"

Should contain subnodes for any of the following relevant hardware resources:

== DDR PHY control

Control registers for this memory controller's DDR PHY.

Required properties:
- compatible     : should contain one of these
	"brcm,brcmstb-ddr-phy-v71.1"
	"brcm,brcmstb-ddr-phy-v72.0"
	"brcm,brcmstb-ddr-phy-v225.1"
	"brcm,brcmstb-ddr-phy-v240.1"
	"brcm,brcmstb-ddr-phy-v240.2"

- reg            : the DDR PHY register range

== DDR SHIMPHY

Control registers for this memory controller's DDR SHIMPHY.

Required properties:
- compatible     : should contain "brcm,brcmstb-ddr-shimphy-v1.0"
- reg            : the DDR SHIMPHY register range

== MEMC DDR control

Sequencer DRAM parameters and control registers. Used for Self-Refresh
Power-Down (SRPD), among other things.

Required properties:
- compatible     : should contain one of these
	"brcm,brcmstb-memc-ddr-rev-b.2.2"
	"brcm,brcmstb-memc-ddr"
- reg            : the MEMC DDR register range

Example:

memory_controllers {
	ranges;
	compatible = "simple-bus";

	memc@0 {
		compatible = "brcm,brcmstb-memc", "simple-bus";
		ranges;

		ddr-phy@f1106000 {
			compatible = "brcm,brcmstb-ddr-phy-v240.1";
			reg = <0xf1106000 0x21c>;
		};

		shimphy@f1108000 {
			compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
			reg = <0xf1108000 0xe4>;
		};

		memc-ddr@f1102000 {
			reg = <0xf1102000 0x800>;
			compatible = "brcm,brcmstb-memc-ddr";
		};
	};

	memc@1 {
		compatible = "brcm,brcmstb-memc", "simple-bus";
		ranges;

		ddr-phy@f1186000 {
			compatible = "brcm,brcmstb-ddr-phy-v240.1";
			reg = <0xf1186000 0x21c>;
		};

		shimphy@f1188000 {
			compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
			reg = <0xf1188000 0xe4>;
		};

		memc-ddr@f1182000 {
			reg = <0xf1182000 0x800>;
			compatible = "brcm,brcmstb-memc-ddr";
		};
	};

	memc@2 {
		compatible = "brcm,brcmstb-memc", "simple-bus";
		ranges;

		ddr-phy@f1206000 {
			compatible = "brcm,brcmstb-ddr-phy-v240.1";
			reg = <0xf1206000 0x21c>;
		};

		shimphy@f1208000 {
			compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
			reg = <0xf1208000 0xe4>;
		};

		memc-ddr@f1202000 {
			reg = <0xf1202000 0x800>;
			compatible = "brcm,brcmstb-memc-ddr";
		};
	};
};