summaryrefslogtreecommitdiffstats
path: root/dts/Bindings/arm/calxeda/l2ecc.txt
blob: 94e642a33db0388c8fcf5fc9f1e7a8d45d4643ff (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Calxeda Highbank L2 cache ECC

Properties:
- compatible : Should be "calxeda,hb-sregs-l2-ecc"
- reg : Address and size for ECC error interrupt clear registers.
- interrupts : Should be single bit error interrupt, then double bit error
	interrupt.

Example:

	sregs@fff3c200 {
		compatible = "calxeda,hb-sregs-l2-ecc";
		reg = <0xfff3c200 0x100>;
		interrupts = <0 71 4  0 72 4>;
	};