summaryrefslogtreecommitdiffstats
path: root/dts/Bindings/arm/freescale/fsl,scu.txt
blob: 10b8459e49f8c22a4ff12c2485b00030dc72df64 (plain) (blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
NXP i.MX System Controller Firmware (SCFW)
--------------------------------------------------------------------

The System Controller Firmware (SCFW) is a low-level system function
which runs on a dedicated Cortex-M core to provide power, clock, and
resource management. It exists on some i.MX8 processors. e.g. i.MX8QM
(QM, QP), and i.MX8QX (QXP, DX).

The AP communicates with the SC using a multi-ported MU module found
in the LSIO subsystem. The current definition of this MU module provides
5 remote AP connections to the SC to support up to 5 execution environments
(TZ, HV, standard Linux, etc.). The SC side of this MU module interfaces
with the LSIO DSC IP bus. The SC firmware will communicate with this MU
using the MSI bus.

System Controller Device Node:
============================================================

The scu node with the following properties shall be under the /firmware/ node.

Required properties:
-------------------
- compatible:	should be "fsl,imx-scu".
- mbox-names:	should include "tx0", "tx1", "tx2", "tx3",
			       "rx0", "rx1", "rx2", "rx3";
		include "gip3" if want to support general MU interrupt.
- mboxes:	List of phandle of 4 MU channels for tx, 4 MU channels for
		rx, and 1 optional MU channel for general interrupt.
		All MU channels must be in the same MU instance.
		Cross instances are not allowed. The MU instance can only
		be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users need
		to make sure use the one which is not conflict with other
		execution environments. e.g. ATF.
		Note:
		Channel 0 must be "tx0" or "rx0".
		Channel 1 must be "tx1" or "rx1".
		Channel 2 must be "tx2" or "rx2".
		Channel 3 must be "tx3" or "rx3".
		General interrupt rx channel must be "gip3".
		e.g.
		mboxes = <&lsio_mu1 0 0
			  &lsio_mu1 0 1
			  &lsio_mu1 0 2
			  &lsio_mu1 0 3
			  &lsio_mu1 1 0
			  &lsio_mu1 1 1
			  &lsio_mu1 1 2
			  &lsio_mu1 1 3
			  &lsio_mu1 3 3>;
		See Documentation/devicetree/bindings/mailbox/fsl,mu.yaml
		for detailed mailbox binding.

Note: Each mu which supports general interrupt should have an alias correctly
numbered in "aliases" node.
e.g.
aliases {
	mu1 = &lsio_mu1;
};

i.MX SCU Client Device Node:
============================================================

Client nodes are maintained as children of the relevant IMX-SCU device node.

Power domain bindings based on SCU Message Protocol
------------------------------------------------------------

This binding for the SCU power domain providers uses the generic power
domain binding[2].

Required properties:
- compatible:		Should be one of:
			  "fsl,imx8qm-scu-pd",
			  "fsl,imx8qxp-scu-pd"
			followed by "fsl,scu-pd"

- #power-domain-cells:	Must be 1. Contains the Resource ID used by
			SCU commands.
			See detailed Resource ID list from:
			include/dt-bindings/firmware/imx/rsrc.h

Clock bindings based on SCU Message Protocol
------------------------------------------------------------

This binding uses the common clock binding[1].

Required properties:
- compatible:		Should be one of:
			  "fsl,imx8qm-clock"
			  "fsl,imx8qxp-clock"
			followed by "fsl,scu-clk"
- #clock-cells:		Should be 1. Contains the Clock ID value.
- clocks:		List of clock specifiers, must contain an entry for
			each required entry in clock-names
- clock-names:		Should include entries "xtal_32KHz", "xtal_24MHz"

The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell.

See the full list of clock IDs from:
include/dt-bindings/clock/imx8qxp-clock.h

Pinctrl bindings based on SCU Message Protocol
------------------------------------------------------------

This binding uses the i.MX common pinctrl binding[3].

Required properties:
- compatible:		Should be one of:
			"fsl,imx8qm-iomuxc",
			"fsl,imx8qxp-iomuxc",
			"fsl,imx8dxl-iomuxc".

Required properties for Pinctrl sub nodes:
- fsl,pins:		Each entry consists of 3 integers which represents
			the mux and config setting for one pin. The first 2
			integers <pin_id mux_mode> are specified using a
			PIN_FUNC_ID macro, which can be found in
			<dt-bindings/pinctrl/pads-imx8qm.h>,
			<dt-bindings/pinctrl/pads-imx8qxp.h>,
			<dt-bindings/pinctrl/pads-imx8dxl.h>.
			The last integer CONFIG is the pad setting value like
			pull-up on this pin.

			Please refer to i.MX8QXP Reference Manual for detailed
			CONFIG settings.

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/power/power-domain.yaml
[3] Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt

RTC bindings based on SCU Message Protocol
------------------------------------------------------------

Required properties:
- compatible: should be "fsl,imx8qxp-sc-rtc";

OCOTP bindings based on SCU Message Protocol
------------------------------------------------------------
Required properties:
- compatible:		Should be one of:
			"fsl,imx8qm-scu-ocotp",
			"fsl,imx8qxp-scu-ocotp".
- #address-cells:	Must be 1. Contains byte index
- #size-cells:		Must be 1. Contains byte length

Optional Child nodes:

- Data cells of ocotp:
  Detailed bindings are described in bindings/nvmem/nvmem.txt

Watchdog bindings based on SCU Message Protocol
------------------------------------------------------------

Required properties:
- compatible: should be:
              "fsl,imx8qxp-sc-wdt"
              followed by "fsl,imx-sc-wdt";
Optional properties:
- timeout-sec: contains the watchdog timeout in seconds.

SCU key bindings based on SCU Message Protocol
------------------------------------------------------------

Required properties:
- compatible: should be:
              "fsl,imx8qxp-sc-key"
              followed by "fsl,imx-sc-key";
- linux,keycodes: See Documentation/devicetree/bindings/input/input.yaml

Thermal bindings based on SCU Message Protocol
------------------------------------------------------------

Required properties:
- compatible:			Should be :
				  "fsl,imx8qxp-sc-thermal"
				followed by "fsl,imx-sc-thermal";

- #thermal-sensor-cells:	See Documentation/devicetree/bindings/thermal/thermal.txt
				for a description.

Example (imx8qxp):
-------------
aliases {
	mu1 = &lsio_mu1;
};

lsio_mu1: mailbox@5d1c0000 {
	...
	#mbox-cells = <2>;
};

firmware {
	scu {
		compatible = "fsl,imx-scu";
		mbox-names = "tx0", "tx1", "tx2", "tx3",
			     "rx0", "rx1", "rx2", "rx3",
			     "gip3";
		mboxes = <&lsio_mu1 0 0
			  &lsio_mu1 0 1
			  &lsio_mu1 0 2
			  &lsio_mu1 0 3
			  &lsio_mu1 1 0
			  &lsio_mu1 1 1
			  &lsio_mu1 1 2
			  &lsio_mu1 1 3
			  &lsio_mu1 3 3>;

		clk: clk {
			compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
			#clock-cells = <1>;
		};

		iomuxc {
			compatible = "fsl,imx8qxp-iomuxc";

			pinctrl_lpuart0: lpuart0grp {
				fsl,pins = <
					SC_P_UART0_RX_ADMA_UART0_RX	0x06000020
					SC_P_UART0_TX_ADMA_UART0_TX	0x06000020
				>;
			};
			...
		};

		ocotp: imx8qx-ocotp {
			compatible = "fsl,imx8qxp-scu-ocotp";
			#address-cells = <1>;
			#size-cells = <1>;

			fec_mac0: mac@2c4 {
				reg = <0x2c4 8>;
			};
		};

		pd: imx8qx-pd {
			compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";
			#power-domain-cells = <1>;
		};

		rtc: rtc {
			compatible = "fsl,imx8qxp-sc-rtc";
		};

		scu_key: scu-key {
			compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
			linux,keycodes = <KEY_POWER>;
		};

		watchdog {
			compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
			timeout-sec = <60>;
		};

		tsens: thermal-sensor {
			compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal";
			#thermal-sensor-cells = <1>;
		};
	};
};

serial@5a060000 {
	...
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart0>;
	clocks = <&clk IMX8QXP_UART0_CLK>,
		 <&clk IMX8QXP_UART0_IPG_CLK>;
	clock-names = "per", "ipg";
	power-domains = <&pd IMX_SC_R_UART_0>;
};