dts/Bindings/ata/allwinner,sun8i-r40-ahci.yaml


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67

# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/allwinner,sun8i-r40-ahci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner R40 AHCI SATA Controller

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

properties:
  compatible:
    const: allwinner,sun8i-r40-ahci

  reg:
    maxItems: 1

  clocks:
    items:
      - description: AHCI Bus Clock
      - description: AHCI Module Clock

  interrupts:
    maxItems: 1

  resets:
    maxItems: 1

  reset-names:
    const: ahci

  ahci-supply:
    description: Regulator for the AHCI controller

  phy-supply:
    description: Regulator for the SATA PHY power

required:
  - compatible
  - reg
  - clocks
  - interrupts
  - resets
  - reset-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/sun8i-r40-ccu.h>
    #include <dt-bindings/reset/sun8i-r40-ccu.h>

    ahci: sata@1c18000 {
        compatible = "allwinner,sun8i-r40-ahci";
        reg = <0x01c18000 0x1000>;
        interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
        resets = <&ccu RST_BUS_SATA>;
        reset-names = "ahci";
        ahci-supply = <&reg_dldo4>;
        phy-supply = <&reg_eldo3>;
    };

...