summaryrefslogtreecommitdiffstats
path: root/dts/Bindings/clock/hi3670-clock.txt
blob: 66f3697eca7877776a4c769278ce71b9fbcaae65 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
* Hisilicon Hi3670 Clock Controller

The Hi3670 clock controller generates and supplies clock to various
controllers within the Hi3670 SoC.

Required Properties:

- compatible: the compatible should be one of the following strings to
	indicate the clock controller functionality.

	- "hisilicon,hi3670-crgctrl"
	- "hisilicon,hi3670-pctrl"
	- "hisilicon,hi3670-pmuctrl"
	- "hisilicon,hi3670-sctrl"
	- "hisilicon,hi3670-iomcu"
	- "hisilicon,hi3670-media1-crg"
	- "hisilicon,hi3670-media2-crg"

- reg: physical base address of the controller and length of memory mapped
  region.

- #clock-cells: should be 1.

Each clock is assigned an identifier and client nodes use this identifier
to specify the clock which they consume.

All these identifier could be found in <dt-bindings/clock/hi3670-clock.h>.

Examples:
	crg_ctrl: clock-controller@fff35000 {
		compatible = "hisilicon,hi3670-crgctrl", "syscon";
		reg = <0x0 0xfff35000 0x0 0x1000>;
		#clock-cells = <1>;
	};

	uart0: serial@fdf02000 {
		compatible = "arm,pl011", "arm,primecell";
		reg = <0x0 0xfdf02000 0x0 0x1000>;
		interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&crg_ctrl HI3670_CLK_GATE_UART0>,
			 <&crg_ctrl HI3670_PCLK>;
		clock-names = "uartclk", "apb_pclk";
	};