summaryrefslogtreecommitdiffstats
path: root/dts/Bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
blob: 56f111bd3e456619ae872fd49825f48b11604c02 (plain) (blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
* Renesas R-Car Gen2 Clock Pulse Generator (CPG)

The CPG generates core clocks for the R-Car Gen2 SoCs. It includes three PLLs
and several fixed ratio dividers.

Required Properties:

  - compatible: Must be one of
    - "renesas,r8a7790-cpg-clocks" for the r8a7790 CPG
    - "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG
    - "renesas,r8a7793-cpg-clocks" for the r8a7793 CPG
    - "renesas,r8a7794-cpg-clocks" for the r8a7794 CPG
    and "renesas,rcar-gen2-cpg-clocks" as a fallback.

  - reg: Base address and length of the memory resource used by the CPG

  - clocks: References to the parent clocks: first to the EXTAL clock, second
    to the USB_EXTAL clock
  - #clock-cells: Must be 1
  - clock-output-names: The names of the clocks. Supported clocks are "main",
    "pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1", "z", "rcan", and
    "adsp"


Example
-------

	cpg_clocks: cpg_clocks@e6150000 {
		compatible = "renesas,r8a7790-cpg-clocks",
			     "renesas,rcar-gen2-cpg-clocks";
		reg = <0 0xe6150000 0 0x1000>;
		clocks = <&extal_clk &usb_extal_clk>;
		#clock-cells = <1>;
		clock-output-names = "main", "pll0, "pll1", "pll3",
				     "lb", "qspi", "sdh", "sd0", "sd1", "z",
				     "rcan", "adsp";
	};