summaryrefslogtreecommitdiffstats
path: root/dts/Bindings/clock/st/st,clkgen-divmux.txt
blob: 6247652044a0b0f528ba05da9954be7c4d24a99e (plain) (blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
Binding for a ST divider and multiplexer clock driver.

This binding uses the common clock binding[1].
Base address is located to the parent node. See clock binding[2]

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt

Required properties:

- compatible : shall be:
	"st,clkgena-divmux-c65-hs",	"st,clkgena-divmux"
	"st,clkgena-divmux-c65-ls",	"st,clkgena-divmux"
	"st,clkgena-divmux-c32-odf0",	"st,clkgena-divmux"
	"st,clkgena-divmux-c32-odf1",	"st,clkgena-divmux"
	"st,clkgena-divmux-c32-odf2",	"st,clkgena-divmux"
	"st,clkgena-divmux-c32-odf3",	"st,clkgena-divmux"

- #clock-cells : From common clock binding; shall be set to 1.

- clocks : From common clock binding

- clock-output-names : From common clock binding.

Example:

	clockgen-a@fd345000 {
		reg = <0xfd345000 0xb50>;

		clk_m_a1_div1: clk-m-a1-div1 {
			#clock-cells = <1>;
			compatible = "st,clkgena-divmux-c32-odf1",
				     "st,clkgena-divmux";

			clocks = <&clk_m_a1_osc_prediv>,
				 <&clk_m_a1_pll0 1>, /* PLL0 PHI1 */
				 <&clk_m_a1_pll1 1>; /* PLL1 PHI1 */

			clock-output-names = "clk-m-rx-icn-ts",
					     "clk-m-rx-icn-vdp-0",
					     "", /* unused */
					     "clk-m-prv-t1-bus",
					     "clk-m-icn-reg-12",
					     "clk-m-icn-reg-10",
					     "", /* unused */
					     "clk-m-icn-st231";
		};
	};