summaryrefslogtreecommitdiffstats
path: root/dts/Bindings/display/rockchip/cdn-dp-rockchip.txt
blob: 8df7d2e393d62e723db0feade13370a52e309ae5 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
Rockchip RK3399 specific extensions to the cdn Display Port
================================

Required properties:
- compatible: must be "rockchip,rk3399-cdn-dp"

- reg: physical base address of the controller and length

- clocks: from common clock binding: handle to dp clock.

- clock-names: from common clock binding:
	       Required elements: "core-clk" "pclk" "spdif" "grf"

- resets : a list of phandle + reset specifier pairs
- reset-names : string of reset names
		Required elements: "apb", "core", "dptx", "spdif"
- power-domains : power-domain property defined with a phandle
		  to respective power domain.
- assigned-clocks: main clock, should be <&cru SCLK_DP_CORE>
- assigned-clock-rates : the DP core clk frequency, shall be: 100000000

- rockchip,grf: this soc should set GRF regs, so need get grf here.

- ports: contain a port nodes with endpoint definitions as defined in
	 Documentation/devicetree/bindings/media/video-interfaces.txt.
	 contained 2 endpoints, connecting to the output of vop.

- phys: from general PHY binding: the phandle for the PHY device.

- extcon: extcon specifier for the Power Delivery

- #sound-dai-cells = it must be 1 if your system is using 2 DAIs: I2S, SPDIF

-------------------------------------------------------------------------------

Example:
	cdn_dp: dp@fec00000 {
		compatible = "rockchip,rk3399-cdn-dp";
		reg = <0x0 0xfec00000 0x0 0x100000>;
		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
			 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
		clock-names = "core-clk", "pclk", "spdif", "grf";
		assigned-clocks = <&cru SCLK_DP_CORE>;
		assigned-clock-rates = <100000000>;
		power-domains = <&power RK3399_PD_HDCP>;
		phys = <&tcphy0_dp>, <&tcphy1_dp>;
		resets = <&cru SRST_DPTX_SPDIF_REC>;
		reset-names = "spdif";
		extcon = <&fusb0>, <&fusb1>;
		rockchip,grf = <&grf>;
		#address-cells = <1>;
		#size-cells = <0>;
		#sound-dai-cells = <1>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			dp_in: port {
				#address-cells = <1>;
				#size-cells = <0>;
				dp_in_vopb: endpoint@0 {
					reg = <0>;
					remote-endpoint = <&vopb_out_dp>;
				};

				dp_in_vopl: endpoint@1 {
					reg = <1>;
					remote-endpoint = <&vopl_out_dp>;
				};
			};
		};
	};