summaryrefslogtreecommitdiffstats
path: root/dts/Bindings/interrupt-controller/renesas,rza1-irqc.txt
blob: 727b7e4cd6e01110f46a34eaca05b1c7fa33d6e0 (plain) (blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
DT bindings for the Renesas RZ/A1 Interrupt Controller

The RZ/A1 Interrupt Controller is a front-end for the GIC found on Renesas
RZ/A1 and RZ/A2 SoCs:
  - IRQ sense select for 8 external interrupts, 1:1-mapped to 8 GIC SPI
    interrupts,
  - NMI edge select.

Required properties:
  - compatible: Must be "renesas,<soctype>-irqc", and "renesas,rza1-irqc" as
		fallback.
		Examples with soctypes are:
		  - "renesas,r7s72100-irqc" (RZ/A1H)
		  - "renesas,r7s9210-irqc" (RZ/A2M)
  - #interrupt-cells: Must be 2 (an interrupt index and flags, as defined
				 in interrupts.txt in this directory)
  - #address-cells: Must be zero
  - interrupt-controller: Marks the device as an interrupt controller
  - reg: Base address and length of the memory resource used by the interrupt
         controller
  - interrupt-map: Specifies the mapping from external interrupts to GIC
		   interrupts
  - interrupt-map-mask: Must be <7 0>

Example:

	irqc: interrupt-controller@fcfef800 {
		compatible = "renesas,r7s72100-irqc", "renesas,rza1-irqc";
		#interrupt-cells = <2>;
		#address-cells = <0>;
		interrupt-controller;
		reg = <0xfcfef800 0x6>;
		interrupt-map =
			<0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
			<1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
			<2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
			<3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
			<4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
			<5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
			<6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
			<7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-map-mask = <7 0>;
	};