summaryrefslogtreecommitdiffstats
path: root/dts/Bindings/mips/cavium/ciu.txt
blob: 2c2d0746b43d1cf9e86ecc0b5cdd33121b266edf (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
* Central Interrupt Unit

Properties:
- compatible: "cavium,octeon-3860-ciu"

  Compatibility with all cn3XXX, cn5XXX and cn63XX SOCs.

- interrupt-controller:  This is an interrupt controller.

- reg: The base address of the CIU's register bank.

- #interrupt-cells: Must be <2>.  The first cell is the bank within
   the CIU and may have a value of 0 or 1.  The second cell is the bit
   within the bank and may have a value between 0 and 63.

Example:
	interrupt-controller@1070000000000 {
		compatible = "cavium,octeon-3860-ciu";
		interrupt-controller;
		/* Interrupts are specified by two parts:
		 * 1) Controller register (0 or 1)
		 * 2) Bit within the register (0..63)
		 */
		#interrupt-cells = <2>;
		reg = <0x10700 0x00000000 0x0 0x7000>;
	};