summaryrefslogtreecommitdiffstats
path: root/dts/Bindings/mips/cavium/ciu3.txt
blob: 616862ad2b71dba58a6658a4b8ed116fa6ea703e (plain) (blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
* Central Interrupt Unit v3

Properties:
- compatible: "cavium,octeon-7890-ciu3"

  Compatibility with 78XX and 73XX SOCs.

- interrupt-controller:  This is an interrupt controller.

- reg: The base address of the CIU's register bank.

- #interrupt-cells: Must be <2>.  The first cell is source number.
  The second cell indicates the triggering semantics, and may have a
  value of either 4 for level semantics, or 1 for edge semantics.

Example:
	interrupt-controller@1010000000000 {
		compatible = "cavium,octeon-7890-ciu3";
		interrupt-controller;
		/* Interrupts are specified by two parts:
		 * 1) Source number (20 significant bits)
		 * 2) Trigger type: (4 == level, 1 == edge)
		 */
		#address-cells = <0>;
		#interrupt-cells = <2>;
		reg = <0x10100 0x00000000 0x0 0xb0000000>;
	};