summaryrefslogtreecommitdiffstats
path: root/dts/Bindings/mips/img/xilfpga.txt
blob: 57e7ee942166fb6b0092202c8016a6599a2017a1 (plain) (blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
Imagination University Program MIPSfpga
=======================================

Under the Imagination University Program, a microAptiv UP core has been
released for academic usage.

As we are dealing with a MIPS core instantiated on an FPGA, specifications
are fluid and can be varied in RTL.

This binding document is provided as baseline guidance for the example
project provided by IMG.

The example project runs on the Nexys4DDR board by Digilent powered by
the ARTIX-7 FPGA by Xilinx.

Relevant details about the example project and the Nexys4DDR board:

- microAptiv UP core m14Kc
- 50MHz clock speed
- 128Mbyte DDR RAM	at 0x0000_0000
- 8Kbyte RAM		at 0x1000_0000
- axi_intc		at 0x1020_0000
- axi_uart16550		at 0x1040_0000
- axi_gpio		at 0x1060_0000
- axi_i2c		at 0x10A0_0000
- custom_gpio		at 0x10C0_0000
- axi_ethernetlite	at 0x10E0_0000
- 8Kbyte BootRAM	at 0x1FC0_0000

Required properties:
--------------------
 - compatible: Must include "digilent,nexys4ddr","img,xilfpga".

CPU nodes:
----------
A "cpus" node is required.  Required properties:
 - #address-cells: Must be 1.
 - #size-cells: Must be 0.
A CPU sub-node is also required for at least CPU 0. Required properties:
 - device_type: Must be "cpu".
 - compatible: Must be "mips,m14Kc".
 - reg: Must be <0>.
 - clocks: phandle to ext clock for fixed-clock received by MIPS core.

Example:

	compatible = "img,xilfpga","digilent,nexys4ddr";
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "mips,m14Kc";
			reg = <0>;
			clocks	= <&ext>;
		};
	};

	ext: ext {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <50000000>;
	};

Boot protocol:
--------------

The BootRAM is a writeable "RAM" in FPGA at 0x1FC0_0000.
This is for easy reprogrammibility via JTAG.

The BootRAM initializes the cache and the axi_uart peripheral.

DDR initialization is already handled by a HW IP block.

When the example project bitstream is loaded, the cpu_reset button
needs to be pressed.

The bootram initializes the cache and axi_uart.
Then outputs MIPSFPGA\n\r on the serial port on the Nexys4DDR board.

At this point, the board is ready to load the Linux kernel
vmlinux file via JTAG.