summaryrefslogtreecommitdiffstats
path: root/dts/Bindings/mmc/sdhci-pxa.txt
blob: 3d1b449d6097d4c71030e18b8ac73a8a283d4453 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
* Marvell sdhci-pxa v2/v3 controller

This file documents differences between the core properties in mmc.txt
and the properties used by the sdhci-pxav2 and sdhci-pxav3 drivers.

Required properties:
- compatible: Should be "mrvl,pxav2-mmc", "mrvl,pxav3-mmc" or
  "marvell,armada-380-sdhci".
- reg:
  * for "mrvl,pxav2-mmc" and "mrvl,pxav3-mmc", one register area for
    the SDHCI registers.

  * for "marvell,armada-380-sdhci", three register areas. The first
    one for the SDHCI registers themselves, the second one for the
    AXI/Mbus bridge registers of the SDHCI unit, the third one for the
    SDIO3 Configuration register
- reg names: should be "sdhci", "mbus", "conf-sdio3". only mandatory
  for "marvell,armada-380-sdhci"
- clocks: Array of clocks required for SDHCI; requires at least one for
    I/O clock.
- clock-names: Array of names corresponding to clocks property; shall be
    "io" for I/O clock and "core" for optional core clock.

Optional properties:
- mrvl,clk-delay-cycles: Specify a number of cycles to delay for tuning.

Example:

sdhci@d4280800 {
	compatible = "mrvl,pxav3-mmc";
	reg = <0xd4280800 0x800>;
	bus-width = <8>;
	interrupts = <27>;
	clocks = <&chip CLKID_SDIO1XIN>, <&chip CLKID_SDIO1>;
	clock-names = "io", "core";
	non-removable;
	mrvl,clk-delay-cycles = <31>;
};

sdhci@d8000 {
	compatible = "marvell,armada-380-sdhci";
	reg-names = "sdhci", "mbus", "conf-sdio3";
	reg = <0xd8000 0x1000>,
		<0xdc000 0x100>;
		<0x18454 0x4>;
	interrupts = <0 25 0x4>;
	clocks = <&gateclk 17>;
	clock-names = "io";
	mrvl,clk-delay-cycles = <0x1F>;
};