summaryrefslogtreecommitdiffstats
path: root/dts/Bindings/net/macb.txt
blob: b5a42df4c9281d20c27cb726b0fac57ff58187c3 (plain) (blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
* Cadence MACB/GEM Ethernet controller

Required properties:
- compatible: Should be "cdns,[<chip>-]{macb|gem}"
  Use "cdns,at91rm9200-emac" Atmel at91rm9200 SoC.
  Use "cdns,at91sam9260-macb" for Atmel at91sam9 SoCs or the 10/100Mbit IP
  available on sama5d3 SoCs.
  Use "cdns,np4-macb" for NP4 SoC devices.
  Use "cdns,at32ap7000-macb" for other 10/100 usage or use the generic form: "cdns,macb".
  Use "cdns,pc302-gem" for Picochip picoXcell pc302 and later devices based on
  the Cadence GEM, or the generic form: "cdns,gem".
  Use "atmel,sama5d2-gem" for the GEM IP (10/100) available on Atmel sama5d2 SoCs.
  Use "atmel,sama5d3-gem" for the Gigabit IP available on Atmel sama5d3 SoCs.
  Use "atmel,sama5d4-gem" for the GEM IP (10/100) available on Atmel sama5d4 SoCs.
  Use "cdns,zynq-gem" Xilinx Zynq-7xxx SoC.
  Use "cdns,zynqmp-gem" for Zynq Ultrascale+ MPSoC.
  Or the generic form: "cdns,emac".
- reg: Address and length of the register set for the device
- interrupts: Should contain macb interrupt
- phy-mode: See ethernet.txt file in the same directory.
- clock-names: Tuple listing input clock names.
	Required elements: 'pclk', 'hclk'
	Optional elements: 'tx_clk'
- clocks: Phandles to input clocks.

Optional properties for PHY child node:
- reset-gpios : Should specify the gpio for phy reset
- magic-packet : If present, indicates that the hardware supports waking
  up via magic packet.

Examples:

	macb0: ethernet@fffc4000 {
		compatible = "cdns,at32ap7000-macb";
		reg = <0xfffc4000 0x4000>;
		interrupts = <21>;
		phy-mode = "rmii";
		local-mac-address = [3a 0e 03 04 05 06];
		clock-names = "pclk", "hclk", "tx_clk";
		clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
		ethernet-phy@1 {
			reg = <0x1>;
			reset-gpios = <&pioE 6 1>;
		};
	};