summaryrefslogtreecommitdiffstats
path: root/dts/Bindings/net/wiznet,w5x00.txt
blob: e9665798c4be639e40c25e78a36fbac0ef1f0d74 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
* Wiznet w5x00

This is a standalone 10/100 MBit Ethernet controller with SPI interface.

For each device connected to a SPI bus, define a child node within
the SPI master node.

Required properties:
- compatible: Should be one of the following strings:
	      "wiznet,w5100"
	      "wiznet,w5200"
	      "wiznet,w5500"
- reg: Specify the SPI chip select the chip is wired to.
- interrupts: Specify the interrupt index within the interrupt controller (referred
              to above in interrupt-parent) and interrupt type. w5x00 natively
              generates falling edge interrupts, however, additional board logic
              might invert the signal.
- pinctrl-names: List of assigned state names, see pinctrl binding documentation.
- pinctrl-0: List of phandles to configure the GPIO pin used as interrupt line,
             see also generic and your platform specific pinctrl binding
             documentation.

Optional properties:
- spi-max-frequency: Maximum frequency of the SPI bus when accessing the w5500.
  According to the w5500 datasheet, the chip allows a maximum of 80 MHz, however,
  board designs may need to limit this value.
- local-mac-address: See ethernet.txt in the same directory.


Example (for Raspberry Pi with pin control stuff for GPIO irq):

&spi {
	ethernet@0: w5500@0 {
		compatible = "wiznet,w5500";
		reg = <0>;
		pinctrl-names = "default";
		pinctrl-0 = <&eth1_pins>;
		interrupt-parent = <&gpio>;
		interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
		spi-max-frequency = <30000000>;
	};
};

&gpio {
	eth1_pins: eth1_pins {
		brcm,pins = <25>;
		brcm,function = <0>; /* in */
		brcm,pull = <0>; /* none */
	};
};