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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/microchip,sparx5-sgpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microsemi/Microchip Serial GPIO controller
maintainers:
- Lars Povlsen <lars.povlsen@microchip.com>
description: |
By using a serial interface, the SIO controller significantly extend
the number of available GPIOs with a minimum number of additional
pins on the device. The primary purpose of the SIO controllers is to
connect control signals from SFP modules and to act as an LED
controller.
properties:
$nodename:
pattern: "^gpio@[0-9a-f]+$"
compatible:
enum:
- microchip,sparx5-sgpio
- mscc,ocelot-sgpio
- mscc,luton-sgpio
"#address-cells":
const: 1
"#size-cells":
const: 0
reg:
maxItems: 1
clocks:
maxItems: 1
microchip,sgpio-port-ranges:
description: This is a sequence of tuples, defining intervals of
enabled ports in the serial input stream. The enabled ports must
match the hardware configuration in order for signals to be
properly written/read to/from the controller holding
registers. Being tuples, then number of arguments must be
even. The tuples mast be ordered (low, high) and are
inclusive.
$ref: /schemas/types.yaml#/definitions/uint32-matrix
items:
items:
- description: |
"low" indicates start bit number of range
minimum: 0
maximum: 31
- description: |
"high" indicates end bit number of range
minimum: 0
maximum: 31
minItems: 1
maxItems: 32
bus-frequency:
description: The sgpio controller frequency (Hz). This dictates
the serial bitstream speed, which again affects the latency in
getting control signals back and forth between external shift
registers. The speed must be no larger than half the system
clock, and larger than zero.
default: 12500000
resets:
maxItems: 1
reset-names:
items:
- const: switch
patternProperties:
"^gpio@[0-1]$":
type: object
properties:
compatible:
const: microchip,sparx5-sgpio-bank
reg:
description: |
The GPIO bank number. "0" is designates the input pin bank,
"1" the output bank.
maxItems: 1
gpio-controller: true
'#gpio-cells':
description: |
Specifies the pin (port and bit) and flags. Note that the
SGIO pin is defined by *2* numbers, a port number between 0
and 31, and a bit index, 0 to 3. The maximum bit number is
controlled indirectly by the "ngpios" property: (ngpios/32).
const: 3
interrupts:
description: Specifies the sgpio IRQ (in parent controller)
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
description:
Specifies the pin (port and bit) and flags, as defined in
defined in include/dt-bindings/interrupt-controller/irq.h
const: 3
ngpios:
description: The numbers of GPIO's exposed. This must be a
multiple of 32.
minimum: 32
maximum: 128
required:
- compatible
- reg
- gpio-controller
- '#gpio-cells'
- ngpios
additionalProperties: false
additionalProperties: false
required:
- compatible
- reg
- clocks
- microchip,sgpio-port-ranges
- "#address-cells"
- "#size-cells"
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
sgpio2: gpio@1101059c {
#address-cells = <1>;
#size-cells = <0>;
compatible = "microchip,sparx5-sgpio";
clocks = <&sys_clk>;
pinctrl-0 = <&sgpio2_pins>;
pinctrl-names = "default";
reg = <0x1101059c 0x118>;
microchip,sgpio-port-ranges = <0 0>, <16 18>, <28 31>;
bus-frequency = <25000000>;
sgpio_in2: gpio@0 {
reg = <0>;
compatible = "microchip,sparx5-sgpio-bank";
gpio-controller;
#gpio-cells = <3>;
ngpios = <96>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <3>;
};
sgpio_out2: gpio@1 {
compatible = "microchip,sparx5-sgpio-bank";
reg = <1>;
gpio-controller;
#gpio-cells = <3>;
ngpios = <96>;
};
};
|
