dts/src/arm/armada-385-clearfog-gtr-s4.dts


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79

// SPDX-License-Identifier: (GPL-2.0 OR MIT)

#include "armada-385-clearfog-gtr.dtsi"

/ {
	model = "SolidRun Clearfog GTR S4";
};

&sfp0 {
	tx-fault-gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>;
};

&mdio {
	switch0: switch0@4 {
		compatible = "marvell,mv88e6085";
		reg = <4>;
		pinctrl-names = "default";
		pinctrl-0 = <&cf_gtr_switch_reset_pins>;
		reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@1 {
				reg = <1>;
				label = "lan2";
				phy-handle = <&switch0phy0>;
			};

			port@2 {
				reg = <2>;
				label = "lan1";
				phy-handle = <&switch0phy1>;
			};

			port@3 {
				reg = <3>;
				label = "lan4";
				phy-handle = <&switch0phy2>;
			};

			port@4 {
				reg = <4>;
				label = "lan3";
				phy-handle = <&switch0phy3>;
			};

			port@5 {
				reg = <5>;
				label = "cpu";
				ethernet = <&eth1>;
			};

		};

		mdio {
			#address-cells = <1>;
			#size-cells = <0>;

			switch0phy0: switch0phy0@11 {
				reg = <0x11>;
			};

			switch0phy1: switch0phy1@12 {
				reg = <0x12>;
			};

			switch0phy2: switch0phy2@13 {
				reg = <0x13>;
			};

			switch0phy3: switch0phy3@14 {
				reg = <0x14>;
			};
		};

	};
};