summaryrefslogtreecommitdiffstats
path: root/dts/src/arm/imx35-pdk.dts
blob: ddce0a844758b3a5836c3d240f0f13bff6a68f4a (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
// Copyright 2014 Freescale Semiconductor, Inc.

/dts-v1/;
#include "imx35.dtsi"

/ {
	model = "Freescale i.MX35 Product Development Kit";
	compatible = "fsl,imx35-pdk", "fsl,imx35";

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x8000000>,
		      <0x90000000 0x8000000>;
	};
};

&esdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_esdhc1>;
	status = "okay";
};

&iomuxc {
	imx35-pdk {
		pinctrl_esdhc1: esdhc1grp {
			fsl,pins = <
				MX35_PAD_SD1_CMD__ESDHC1_CMD		0x80000000
				MX35_PAD_SD1_CLK__ESDHC1_CLK		0x80000000
				MX35_PAD_SD1_DATA0__ESDHC1_DAT0		0x80000000
				MX35_PAD_SD1_DATA1__ESDHC1_DAT1		0x80000000
				MX35_PAD_SD1_DATA2__ESDHC1_DAT2		0x80000000
				MX35_PAD_SD1_DATA3__ESDHC1_DAT3		0x80000000
			>;
		};

		pinctrl_uart1: uart1grp {
			fsl,pins = <
				MX35_PAD_TXD1__UART1_TXD_MUX		0x1c5
				MX35_PAD_RXD1__UART1_RXD_MUX		0x1c5
				MX35_PAD_CTS1__UART1_CTS		0x1c5
				MX35_PAD_RTS1__UART1_RTS		0x1c5
			>;
		};
	};
};

&nfc {
	nand-bus-width = <16>;
	nand-ecc-mode = "hw";
	nand-on-flash-bbt;
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	uart-has-rtscts;
	status = "okay";
};