summaryrefslogtreecommitdiffstats
path: root/dts/src/arm/imx6qdl-sr-som.dtsi
blob: 7e4e5fd0143a1272b9f83067f7b2f02339193533 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
/*
 * Copyright (C) 2013,2014 Russell King
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License
 *     version 2 as published by the Free Software Foundation.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */
#include <dt-bindings/gpio/gpio.h>

/ {
	vcc_3v3: regulator-vcc-3v3 {
		compatible = "regulator-fixed";
		regulator-always-on;
		regulator-name = "vcc_3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};
};

&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_microsom_enet_ar8035>;
	phy-mode = "rgmii-id";
	phy-reset-duration = <2>;
	phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		/*
		 * The PHY can appear at either address 0 or 4 due to the
		 * configuration (LED) pin not being pulled sufficiently.
		 */
		ethernet-phy@0 {
			reg = <0>;
			qca,clk-out-frequency = <125000000>;
		};

		ethernet-phy@4 {
			reg = <4>;
			qca,clk-out-frequency = <125000000>;
		};
	};
};

&iomuxc {
	microsom {
		pinctrl_microsom_enet_ar8035: microsom-enet-ar8035 {
			fsl,pins = <
				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b8b0
				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
				/* AR8035 reset */
				MX6QDL_PAD_KEY_ROW4__GPIO4_IO15		0x130b0
				/* AR8035 interrupt */
				MX6QDL_PAD_DI0_PIN2__GPIO4_IO18		0x1b0b0
				/* GPIO16 -> AR8035 25MHz */
				MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0b0
				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x13030
				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
				/* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x0a0b1
				/* AR8035 pin strapping: IO voltage: pull up */
				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
				/* AR8035 pin strapping: PHYADDR#0: pull down */
				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x13030
				/* AR8035 pin strapping: PHYADDR#1: pull down */
				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x13030
				/* AR8035 pin strapping: MODE#1: pull up */
				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
				/* AR8035 pin strapping: MODE#3: pull up */
				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
				/* AR8035 pin strapping: MODE#0: pull down */
				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x13030

				/*
				 * As the RMII pins are also connected to RGMII
				 * so that an AR8030 can be placed, set these
				 * to high-z with the same pulls as above.
				 * Use the GPIO settings to avoid changing the
				 * input select registers.
				 */
				MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25	0x03000
				MX6QDL_PAD_ENET_RXD0__GPIO1_IO27	0x03000
				MX6QDL_PAD_ENET_RXD1__GPIO1_IO26	0x03000
			>;
		};

		pinctrl_microsom_uart1: microsom-uart1 {
			fsl,pins = <
				MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA	0x1b0b1
				MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA	0x1b0b1
			>;
		};
	};
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_microsom_uart1>;
	status = "okay";
};