summaryrefslogtreecommitdiffstats
path: root/dts/src/arm64/freescale/imx8mn-evk.dtsi
blob: 85e65f8719ea5917ede0507bf18e9b83811af330 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2019 NXP
 */

#include <dt-bindings/usb/pd.h>
#include "imx8mn.dtsi"

/ {
	chosen {
		stdout-path = &uart2;
	};

	gpio-leds {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_led>;

		status {
			label = "yellow:status";
			gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
			default-state = "on";
		};
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0x0 0x40000000 0 0x80000000>;
	};

	reg_usdhc2_vmmc: regulator-usdhc2 {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
		regulator-name = "VSD_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	ir-receiver {
		compatible = "gpio-ir-receiver";
		gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_ir>;
		linux,autosuspend-period = <125>;
	};

	wm8524: audio-codec {
		#sound-dai-cells = <0>;
		compatible = "wlf,wm8524";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_wlf>;
		wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
		clocks = <&clk IMX8MN_CLK_SAI3_ROOT>;
		clock-names = "mclk";
	};

	sound-wm8524 {
		compatible = "fsl,imx-audio-wm8524";
		model = "wm8524-audio";
		audio-cpu = <&sai3>;
		audio-codec = <&wm8524>;
		audio-asrc = <&easrc>;
		audio-routing =
			"Line Out Jack", "LINEVOUTL",
			"Line Out Jack", "LINEVOUTR";
	};

	sound-spdif {
		compatible = "fsl,imx-audio-spdif";
		model = "imx-spdif";
		spdif-controller = <&spdif1>;
		spdif-out;
		spdif-in;
	};
};

&easrc {
	fsl,asrc-rate  = <48000>;
	status = "okay";
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy0>;
	fsl,magic-packet;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0>;
		};
	};
};

&i2c1 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";
};

&i2c2 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";

	ptn5110: tcpc@50 {
		compatible = "nxp,ptn5110";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_typec1>;
		reg = <0x50>;
		interrupt-parent = <&gpio2>;
		interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
		status = "okay";

		port {
			typec1_dr_sw: endpoint {
				remote-endpoint = <&usb1_drd_sw>;
			};
		};

		typec1_con: connector {
			compatible = "usb-c-connector";
			label = "USB-C";
			power-role = "dual";
			data-role = "dual";
			try-power-role = "sink";
			source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
			sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
				     PDO_VAR(5000, 20000, 3000)>;
			op-sink-microwatt = <15000000>;
			self-powered;
		};
	};
};

&i2c3 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";

	pca6416: gpio@20 {
		compatible = "ti,tca6416";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
	};
};

&sai3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai3>;
	assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
	assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
	assigned-clock-rates = <24576000>;
	fsl,sai-mclk-direction-output;
	status = "okay";
};

&snvs_pwrkey {
	status = "okay";
};

&spdif1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_spdif1>;
	assigned-clocks = <&clk IMX8MN_CLK_SPDIF1>;
	assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
	assigned-clock-rates = <24576000>;
	status = "okay";
};

&uart2 { /* console */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";
};

&usbotg1 {
	dr_mode = "otg";
	hnp-disable;
	srp-disable;
	adp-disable;
	usb-role-switch;
	disable-over-current;
	samsung,picophy-pre-emp-curr-control = <3>;
	samsung,picophy-dc-vol-level-adjust = <7>;
	status = "okay";

	port {
		usb1_drd_sw: endpoint {
			remote-endpoint = <&typec1_dr_sw>;
		};
	};
};

&usdhc2 {
	assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
	assigned-clock-rates = <200000000>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
	cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
	bus-width = <4>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
	status = "okay";
};

&usdhc3 {
	assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
	assigned-clock-rates = <400000000>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	bus-width = <8>;
	non-removable;
	status = "okay";
};

&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	status = "okay";
};

&iomuxc {
	pinctrl_fec1: fec1grp {
		fsl,pins = <
			MX8MN_IOMUXC_ENET_MDC_ENET1_MDC		0x3
			MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO	0x3
			MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3	0x1f
			MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2	0x1f
			MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1	0x1f
			MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0	0x1f
			MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3	0x91
			MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2	0x91
			MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x91
			MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x91
			MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC	0x1f
			MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC	0x91
			MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
			MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
			MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22	0x19
		>;
	};

	pinctrl_gpio_led: gpioledgrp {
		fsl,pins = <
			MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16	0x19
		>;
	};

	pinctrl_gpio_wlf: gpiowlfgrp {
		fsl,pins = <
			MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21	0xd6
		>;
	};

	pinctrl_ir: irgrp {
		fsl,pins = <
			MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13              0x4f
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c3
			MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c3
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3
			MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3
		>;
	};

	pinctrl_i2c3: i2c3grp {
		fsl,pins = <
			MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c3
			MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3
		>;
	};

	pinctrl_pmic: pmicirqgrp {
		fsl,pins = <
			MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x141
		>;
	};

	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
		fsl,pins = <
			MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
		>;
	};

	pinctrl_sai3: sai3grp {
		fsl,pins = <
			MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6
			MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6
			MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6
			MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6
		>;
	};

	pinctrl_spdif1: spdif1grp {
		fsl,pins = <
			MX8MN_IOMUXC_SPDIF_TX_SPDIF1_OUT	0xd6
			MX8MN_IOMUXC_SPDIF_RX_SPDIF1_IN		0xd6
		>;
	};

	pinctrl_typec1: typec1grp {
		fsl,pins = <
			MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11	0x159
		>;
	};

	pinctrl_uart2: uart2grp {
		fsl,pins = <
			MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
			MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
		>;
	};

	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
		fsl,pins = <
			MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x1c4
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
		>;
	};

	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
		fsl,pins = <
			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
		>;
	};

	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
		fsl,pins = <
			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
		>;
	};

	pinctrl_usdhc3: usdhc3grp {
		fsl,pins = <
			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x40000190
			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d0
			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d0
			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d0
			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d0
			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d0
			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d0
			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d0
			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d0
			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d0
			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x190
		>;
	};

	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
		fsl,pins = <
			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x40000194
			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d4
			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d4
			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d4
			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d4
			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d4
			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4
			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d4
			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d4
			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4
			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x194
		>;
	};

	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
		fsl,pins = <
			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x40000196
			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d6
			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d6
			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d6
			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d6
			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d6
			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d6
			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d6
			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d6
			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d6
			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x196
		>;
	};

	pinctrl_wdog: wdoggrp {
		fsl,pins = <
			MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0x166
		>;
	};
};