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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the RZ/G2[MN] HiHope sub board common parts
*
* Copyright (C) 2019 Renesas Electronics Corp.
*/
/ {
aliases {
ethernet0 = &avb;
};
chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
};
backlight {
compatible = "pwm-backlight";
pwms = <&pwm0 0 50000>;
brightness-levels = <0 2 8 16 32 64 128 255>;
default-brightness-level = <6>;
};
};
&avb {
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
phy-handle = <&phy0>;
phy-mode = "rgmii-txid";
status = "okay";
phy0: ethernet-phy@0 {
rxc-skew-ps = <1500>;
reg = <0>;
interrupt-parent = <&gpio2>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
};
};
&can0 {
pinctrl-0 = <&can0_pins>;
pinctrl-names = "default";
status = "okay";
};
&can1 {
pinctrl-0 = <&can1_pins>;
pinctrl-names = "default";
status = "okay";
};
&gpio1 {
/*
* When GP1_20 is LOW LVDS0 is connected to the LVDS connector
* When GP1_20 is HIGH LVDS0 is connected to the LT8918L
*/
lvds-connector-en-gpio {
gpio-hog;
gpios = <20 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "lvds-connector-en-gpio";
};
};
&lvds0 {
/*
* Please include the LVDS panel .dtsi file and uncomment the below line
* to enable LVDS panel connected to RZ/G2[MN] boards.
*/
/* status = "okay"; */
ports {
port@1 {
lvds_connector: endpoint {
};
};
};
};
&pciec0 {
status = "okay";
};
&pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
avb_pins: avb {
mux {
groups = "avb_link", "avb_mdio", "avb_mii";
function = "avb";
};
pins_mdio {
groups = "avb_mdio";
drive-strength = <24>;
};
pins_mii_tx {
pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0",
"PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3";
drive-strength = <12>;
};
};
can0_pins: can0 {
groups = "can0_data_a";
function = "can0";
};
can1_pins: can1 {
groups = "can1_data";
function = "can1";
};
pwm0_pins: pwm0 {
groups = "pwm0";
function = "pwm0";
};
};
&pwm0 {
pinctrl-0 = <&pwm0_pins>;
pinctrl-names = "default";
status = "okay";
};
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