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author | Marco Felsch <m.felsch@pengutronix.de> | 2022-11-15 12:19:00 +0100 |
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committer | Marco Felsch <m.felsch@pengutronix.de> | 2022-11-22 10:05:35 +0100 |
commit | 2da32c5f988e889b483fc51f18731f13a3076294 (patch) | |
tree | 2bb20b776dfe2a84fa0ae29be71ed9f176403cdb | |
parent | 9fbe131953b71f39a8502a40acd7ae9815d37b8e (diff) | |
download | linux-0-day-v6.1/topic/net-phy-reset.tar.gz linux-0-day-v6.1/topic/net-phy-reset.tar.xz |
net: phy: add default gpio assert/deassert delayv6.1/topic/net-phy-reset
There are phy's not mention any assert/deassert delay within their
datasheets but the real world showed that this is not true. They need at
least a few us to be accessible and to readout the register values. So
add a sane default value of 1000us for both assert and deassert to fix
this in a global matter.
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
-rw-r--r-- | drivers/net/phy/phy_device.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c index e2c59461d2b10..ee8d8430ec0b9 100644 --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c @@ -3135,6 +3135,9 @@ fwnode_find_mii_timestamper(struct fwnode_handle *fwnode) return register_mii_timestamper(arg.np, arg.args[0]); } +#define DEFAULT_GPIO_RESET_ASSERT_DELAY_US 1000 +#define DEFAULT_GPIO_RESET_DEASSERT_DELAY_US 1000 + static int phy_device_parse_fwnode(struct phy_device *phydev, struct phy_device_config *config) @@ -3161,8 +3164,11 @@ phy_device_parse_fwnode(struct phy_device *phydev, if (fwnode_property_read_bool(fwnode, "broken-turn-around")) bus->phy_ignore_ta_mask |= 1 << addr; + + phydev->mdio.reset_assert_delay = DEFAULT_GPIO_RESET_ASSERT_DELAY_US; fwnode_property_read_u32(fwnode, "reset-assert-us", &phydev->mdio.reset_assert_delay); + phydev->mdio.reset_deassert_delay = DEFAULT_GPIO_RESET_DEASSERT_DELAY_US; fwnode_property_read_u32(fwnode, "reset-deassert-us", &phydev->mdio.reset_deassert_delay); |