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| author | Marco Felsch <m.felsch@pengutronix.de> | 2022-11-15 12:19:00 +0100 |
|---|---|---|
| committer | Marco Felsch <m.felsch@pengutronix.de> | 2023-04-04 12:48:44 +0200 |
| commit | dd4af2627d5496b53e33b9fc56dba5d0e1aa15da (patch) | |
| tree | 3ef0d34884202a90d7aac0bfd0a2f3060c56f5fc | |
| parent | b1a955ab4d2fcdf8ae54a03fd182d447e027ec66 (diff) | |
| download | linux-0-day-v6.3/topic/net-phy-reset.tar.gz linux-0-day-v6.3/topic/net-phy-reset.tar.xz | |
net: phy: add default gpio assert/deassert delayv6.3/topic/net-phy-reset
There are phy's not mention any assert/deassert delay within their
datasheets but the real world showed that this is not true. They need at
least a few us to be accessible and to readout the register values. So
add a sane default value of 1000us for both assert and deassert to fix
this in a global matter.
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
| -rw-r--r-- | drivers/net/phy/phy_device.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c index e31fbd83e48c0..967d0345738d4 100644 --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c @@ -3197,6 +3197,9 @@ fwnode_find_mii_timestamper(struct fwnode_handle *fwnode) return register_mii_timestamper(arg.np, arg.args[0]); } +#define DEFAULT_GPIO_RESET_ASSERT_DELAY_US 1000 +#define DEFAULT_GPIO_RESET_DEASSERT_DELAY_US 1000 + static int phy_device_parse_fwnode(struct phy_device *phydev, struct phy_device_config *config) @@ -3223,8 +3226,11 @@ phy_device_parse_fwnode(struct phy_device *phydev, if (fwnode_property_read_bool(fwnode, "broken-turn-around")) bus->phy_ignore_ta_mask |= 1 << addr; + + phydev->mdio.reset_assert_delay = DEFAULT_GPIO_RESET_ASSERT_DELAY_US; fwnode_property_read_u32(fwnode, "reset-assert-us", &phydev->mdio.reset_assert_delay); + phydev->mdio.reset_deassert_delay = DEFAULT_GPIO_RESET_DEASSERT_DELAY_US; fwnode_property_read_u32(fwnode, "reset-deassert-us", &phydev->mdio.reset_deassert_delay); |