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author | Thomas Gleixner <tglx@linutronix.de> | 2019-03-29 21:28:58 +0100 |
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committer | Thomas Gleixner <tglx@linutronix.de> | 2019-03-29 21:28:58 +0100 |
commit | 22261fdf68f23df3ddf359642696d6ce98e584fa (patch) | |
tree | 8016316344a17dd8b88ef042a7cfff7f52a10b30 /arch/arm64/boot/dts/renesas/r8a774c0.dtsi | |
parent | 1a9df9e29c2afecf6e3089442d429b377279ca3c (diff) | |
parent | e94d6b7f615e6dfbaf9fba7db6011db561461d0c (diff) | |
download | linux-0-day-22261fdf68f23df3ddf359642696d6ce98e584fa.tar.gz linux-0-day-22261fdf68f23df3ddf359642696d6ce98e584fa.tar.xz |
Merge tag 'perf-urgent-for-mingo-5.1-20190329' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux into perf/urgent
Pull perf/urgent fixes from Arnaldo:
Core libraries:
Jiri Olsa:
- Fix max perf_event_attr.precise_ip detection.
Kan Liang:
- Fix parser error for uncore event alias
Wei Lin:
- Fixup ordering of kernel maps after obtaining the main kernel map address.
Intel PT:
Adrian Hunter:
- Fix TSC slip where A TSC packet can slip past MTC packets so that the
timestamp appears to go backwards.
- Fixes for exported-sql-viewer GUI conversion to python3.
ARM coresight:
Solomon Tan:
- Fix the build by adding a missing case value for enumeration value introduced
in newer library, that now is the required one.
tool headers:
Arnaldo Carvalho de Melo:
- Syncronize kernel headers with the kernel, getting new io_uring and
pidfd_send_signal syscalls so that 'perf trace' can handle them.
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Diffstat (limited to 'arch/arm64/boot/dts/renesas/r8a774c0.dtsi')
-rw-r--r-- | arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index 61a0afb74e631..1ea684af99c4a 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -2,7 +2,7 @@ /* * Device Tree Source for the RZ/G2E (R8A774C0) SoC * - * Copyright (C) 2018 Renesas Electronics Corp. + * Copyright (C) 2018-2019 Renesas Electronics Corp. */ #include <dt-bindings/clock/r8a774c0-cpg-mssr.h> @@ -1150,9 +1150,8 @@ <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, - <&dmac2 0x5b>, <&dmac2 0x5a>; - dma-names = "tx", "rx", "tx", "rx"; + dmas = <&dmac0 0x5b>, <&dmac0 0x5a>; + dma-names = "tx", "rx"; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; resets = <&cpg 202>; status = "disabled"; |