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| author | Sergey Ryazanov <ryazanov.s.a@gmail.com> | 2014-10-29 03:18:41 +0400 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2014-11-24 07:45:27 +0100 |
| commit | 1753e74ed8fa3235174d5baa3421cbf8d693a42d (patch) | |
| tree | bb6b196bb76d05dfb2be056218643ed2c0513baa /arch/mips/ath25/ar5312_regs.h | |
| parent | ba910345034aea52d292bdc26b9c6831ab7b54e8 (diff) | |
| download | linux-0-day-1753e74ed8fa3235174d5baa3421cbf8d693a42d.tar.gz linux-0-day-1753e74ed8fa3235174d5baa3421cbf8d693a42d.tar.xz | |
MIPS: ath25: add interrupts handling routines
Add interrupts initialization and handling routines, also add AHB bus
error interrupt handlers for both SoCs families.
Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com>
Cc: Linux MIPS <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/8240/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/ath25/ar5312_regs.h')
| -rw-r--r-- | arch/mips/ath25/ar5312_regs.h | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/arch/mips/ath25/ar5312_regs.h b/arch/mips/ath25/ar5312_regs.h index ff1201119be05..4b947f967439d 100644 --- a/arch/mips/ath25/ar5312_regs.h +++ b/arch/mips/ath25/ar5312_regs.h @@ -12,6 +12,29 @@ #define __ASM_MACH_ATH25_AR5312_REGS_H /* + * IRQs + */ +#define AR5312_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */ +#define AR5312_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */ +#define AR5312_IRQ_ENET1 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */ +#define AR5312_IRQ_WLAN1 (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */ +#define AR5312_IRQ_MISC (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */ + +/* + * Miscellaneous interrupts, which share IP6. + */ +#define AR5312_MISC_IRQ_TIMER 0 +#define AR5312_MISC_IRQ_AHB_PROC 1 +#define AR5312_MISC_IRQ_AHB_DMA 2 +#define AR5312_MISC_IRQ_GPIO 3 +#define AR5312_MISC_IRQ_UART0 4 +#define AR5312_MISC_IRQ_UART0_DMA 5 +#define AR5312_MISC_IRQ_WATCHDOG 6 +#define AR5312_MISC_IRQ_LOCAL 7 +#define AR5312_MISC_IRQ_SPI 8 +#define AR5312_MISC_IRQ_COUNT 9 + +/* * Address Map * * The AR5312 supports 2 enet MACS, even though many reference boards only |