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| author | Quentin Schulz <quentin.schulz@bootlin.com> | 2018-07-25 14:21:32 +0200 |
|---|---|---|
| committer | Paul Burton <paul.burton@mips.com> | 2018-07-26 10:34:58 -0700 |
| commit | 49e5bb13adc11fe6e2e40f65c04f3a461aea1fec (patch) | |
| tree | f1ea496d1213d3fa975df52be2a883503c4a5b14 /arch/mips/boot | |
| parent | 74a2c0c466284dd537fe467e4c5e3cb8db52a4b2 (diff) | |
| download | linux-0-day-49e5bb13adc11fe6e2e40f65c04f3a461aea1fec.tar.gz linux-0-day-49e5bb13adc11fe6e2e40f65c04f3a461aea1fec.tar.xz | |
MIPS: mscc: ocelot: fix length of memory address space for MIIM
The length of memory address space for MIIM0 is from 0x7107009c to
0x710700bf included which is 36 bytes long in decimal, or 0x24 bytes in
hexadecimal and not 0x36.
Fixes: 49b031690abe ("MIPS: mscc: Add switch to ocelot")
Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/20013/
Cc: robh+dt@kernel.org
Cc: mark.rutland@arm.com
Cc: ralf@linux-mips.org
Cc: jhogan@kernel.org
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: thomas.petazzoni@bootlin.com
Diffstat (limited to 'arch/mips/boot')
| -rw-r--r-- | arch/mips/boot/dts/mscc/ocelot.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi b/arch/mips/boot/dts/mscc/ocelot.dtsi index 4f33dbc673482..7096915f26e0d 100644 --- a/arch/mips/boot/dts/mscc/ocelot.dtsi +++ b/arch/mips/boot/dts/mscc/ocelot.dtsi @@ -184,7 +184,7 @@ #address-cells = <1>; #size-cells = <0>; compatible = "mscc,ocelot-miim"; - reg = <0x107009c 0x36>, <0x10700f0 0x8>; + reg = <0x107009c 0x24>, <0x10700f0 0x8>; interrupts = <14>; status = "disabled"; |