diff options
| author | Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> | 2013-04-01 18:14:28 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2013-04-05 15:10:45 +0200 |
| commit | adb3789264c4e8567113a0e764ad30ce6e8737f3 (patch) | |
| tree | 8cca117e544ee9a6a6586e45ab18b15069bf213e /arch/mips/mm/sc-mips.c | |
| parent | ed1197f9317c960a199f491779e056c572506dd3 (diff) | |
| download | linux-0-day-adb3789264c4e8567113a0e764ad30ce6e8737f3.tar.gz linux-0-day-adb3789264c4e8567113a0e764ad30ce6e8737f3.tar.xz | |
MIPS: Fix ISA level which causes secondary cache init bypassing and more
The commit a96102be70 introduced set_isa() where compatible ISA info is
also set aside from the one gets passed in. It means, for example, 1004K
will have MIPS_CPU_ISA_M32R2/M32R1/II/I flags. This leads to things like
the following inappropriate:
if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
c->isa_level == MIPS_CPU_ISA_M32R2 ||
c->isa_level == MIPS_CPU_ISA_M64R1 ||
c->isa_level == MIPS_CPU_ISA_M64R2)
This patch fixes it.
Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mm/sc-mips.c')
| -rw-r--r-- | arch/mips/mm/sc-mips.c | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c index 93d937b4b1ba6..df96da7e939b5 100644 --- a/arch/mips/mm/sc-mips.c +++ b/arch/mips/mm/sc-mips.c @@ -98,10 +98,8 @@ static inline int __init mips_sc_probe(void) c->scache.flags |= MIPS_CACHE_NOT_PRESENT; /* Ignore anything but MIPSxx processors */ - if (c->isa_level != MIPS_CPU_ISA_M32R1 && - c->isa_level != MIPS_CPU_ISA_M32R2 && - c->isa_level != MIPS_CPU_ISA_M64R1 && - c->isa_level != MIPS_CPU_ISA_M64R2) + if (!(c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 | + MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2))) return 0; /* Does this MIPS32/MIPS64 CPU have a config2 register? */ |