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| author | Dinh Nguyen <dinguyen@kernel.org> | 2018-11-13 12:50:48 -0600 |
|---|---|---|
| committer | Philipp Zabel <p.zabel@pengutronix.de> | 2019-01-07 16:38:50 +0100 |
| commit | b3ca9888f35fa6919569cf27c929dc0ac49e9716 (patch) | |
| tree | 0372e63304427cde5620f8bfc726096a1cae4b89 /drivers/reset/Kconfig | |
| parent | 151f72f493f2605ebbed0198362eed05918ed839 (diff) | |
| download | linux-0-day-b3ca9888f35fa6919569cf27c929dc0ac49e9716.tar.gz linux-0-day-b3ca9888f35fa6919569cf27c929dc0ac49e9716.tar.xz | |
reset: socfpga: add an early reset driver for SoCFPGA
Create a separate reset driver that uses the reset operations in
reset-simple. The reset driver for the SoCFPGA platform needs to
register early in order to be able bring online timers that needed
early in the kernel bootup.
We do not need this early reset driver for Stratix10, because on
arm64, Linux does not need the timers are that in reset. Linux is
able to run just fine with the internal armv8 timer. Thus, we use
a new binding "altr,stratix10-rst-mgr" for the Stratix10 platform.
The Stratix10 platform will continue to use the reset-simple platform
driver, while the 32-bit platforms(Cyclone5/Arria5/Arria10) will use
the early reset driver.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
[p.zabel@pengutronix.de: fixed socfpga of_device_id in reset-simple]
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Diffstat (limited to 'drivers/reset/Kconfig')
| -rw-r--r-- | drivers/reset/Kconfig | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index c21da9fe51ec0..7ee64988faac0 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -109,7 +109,7 @@ config RESET_QCOM_PDC config RESET_SIMPLE bool "Simple Reset Controller Driver" if COMPILE_TEST - default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED + default ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED help This enables a simple reset controller driver for reset lines that that can be asserted and deasserted by toggling bits in a contiguous, @@ -128,6 +128,14 @@ config RESET_STM32MP157 help This enables the RCC reset controller driver for STM32 MPUs. +config RESET_SOCFPGA + bool "SoCFPGA Reset Driver" if COMPILE_TEST && !ARCH_SOCFPGA + default ARCH_SOCFPGA + select RESET_SIMPLE + help + This enables the reset driver for the SoCFPGA ARMv7 platforms. This + driver gets initialized early during platform init calls. + config RESET_SUNXI bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI default ARCH_SUNXI |