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| author | Florian Fainelli <f.fainelli@gmail.com> | 2018-05-11 15:02:42 -0700 |
|---|---|---|
| committer | Florian Fainelli <f.fainelli@gmail.com> | 2018-06-26 15:44:25 -0700 |
| commit | a334e45dcbff66ccbb6085ce5fdc2fcd861cc788 (patch) | |
| tree | 492efe834f653887e29a7063853740074ec6634b /drivers/soc | |
| parent | 77d899631d8aeb2aed0beae24a6e5a7e5c880505 (diff) | |
| download | linux-0-day-a334e45dcbff66ccbb6085ce5fdc2fcd861cc788.tar.gz linux-0-day-a334e45dcbff66ccbb6085ce5fdc2fcd861cc788.tar.xz | |
soc: bcm: brcmstb: Add missing DDR MEMC compatible strings
We would not be matching the following chip/compatible strings
combinations, which would lead to not setting the warm boot flag
correctly, fix that:
7260A0/B0: brcm,brcmstb-memc-ddr-rev-b.2.1
7255A0: brcm,brcmstb-memc-ddr-rev-b.2.3
7278Bx: brcm,brcmstb-memc-ddr-rev-b.3.1
The B2.1 core (which is in 7260 A0 and B0) doesn't have the
SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL setup in the memsys init code, nor
does it have the warm boot flag re-definition on entry. Those changes
were for B2.2 and later MEMSYS cores. Fall back to the previous S2/S3
entry method for these specific chips.
Fixes: 0b741b8234c8 ("soc: bcm: brcmstb: Add support for S2/S3/S5 suspend states (ARM)")
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Diffstat (limited to 'drivers/soc')
| -rw-r--r-- | drivers/soc/bcm/brcmstb/pm/pm-arm.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/soc/bcm/brcmstb/pm/pm-arm.c b/drivers/soc/bcm/brcmstb/pm/pm-arm.c index ade724677238c..a5577dd5eb087 100644 --- a/drivers/soc/bcm/brcmstb/pm/pm-arm.c +++ b/drivers/soc/bcm/brcmstb/pm/pm-arm.c @@ -628,14 +628,26 @@ static const struct of_device_id ddr_shimphy_dt_ids[] = { static const struct of_device_id brcmstb_memc_of_match[] = { { + .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.1", + .data = &ddr_seq, + }, + { .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.2", .data = &ddr_seq_b22, }, { + .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.3", + .data = &ddr_seq_b22, + }, + { .compatible = "brcm,brcmstb-memc-ddr-rev-b.3.0", .data = &ddr_seq_b22, }, { + .compatible = "brcm,brcmstb-memc-ddr-rev-b.3.1", + .data = &ddr_seq_b22, + }, + { .compatible = "brcm,brcmstb-memc-ddr", .data = &ddr_seq, }, |