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| author | Ingo Molnar <mingo@kernel.org> | 2015-05-11 16:05:09 +0200 |
|---|---|---|
| committer | Ingo Molnar <mingo@kernel.org> | 2015-05-11 16:05:09 +0200 |
| commit | 191a66353b22fad8ac89404ab4c929cbe7b0afb2 (patch) | |
| tree | bd7affc4bc640eb42e5ff3285922497285f8fdd7 /include/linux/intel-iommu.h | |
| parent | f5d6a52f511157c7476590532a23b5664b1ed877 (diff) | |
| parent | f21262b8e092a770e39fbd405cc18a0247c3af68 (diff) | |
| download | linux-0-day-191a66353b22fad8ac89404ab4c929cbe7b0afb2.tar.gz linux-0-day-191a66353b22fad8ac89404ab4c929cbe7b0afb2.tar.xz | |
Merge branch 'x86/asm' into x86/apic, to resolve a conflict
Conflicts:
arch/x86/kernel/apic/io_apic.c
arch/x86/kernel/apic/vector.c
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'include/linux/intel-iommu.h')
| -rw-r--r-- | include/linux/intel-iommu.h | 18 |
1 files changed, 15 insertions, 3 deletions
diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h index ecaf3a9378452..0af9b03e2b1c8 100644 --- a/include/linux/intel-iommu.h +++ b/include/linux/intel-iommu.h @@ -115,10 +115,19 @@ static inline void dmar_writeq(void __iomem *addr, u64 val) * Extended Capability Register */ -#define ecap_niotlb_iunits(e) ((((e) >> 24) & 0xff) + 1) +#define ecap_pss(e) ((e >> 35) & 0x1f) +#define ecap_eafs(e) ((e >> 34) & 0x1) +#define ecap_nwfs(e) ((e >> 33) & 0x1) +#define ecap_srs(e) ((e >> 31) & 0x1) +#define ecap_ers(e) ((e >> 30) & 0x1) +#define ecap_prs(e) ((e >> 29) & 0x1) +#define ecap_pasid(e) ((e >> 28) & 0x1) +#define ecap_dis(e) ((e >> 27) & 0x1) +#define ecap_nest(e) ((e >> 26) & 0x1) +#define ecap_mts(e) ((e >> 25) & 0x1) +#define ecap_ecs(e) ((e >> 24) & 0x1) #define ecap_iotlb_offset(e) ((((e) >> 8) & 0x3ff) * 16) -#define ecap_max_iotlb_offset(e) \ - (ecap_iotlb_offset(e) + ecap_niotlb_iunits(e) * 16) +#define ecap_max_iotlb_offset(e) (ecap_iotlb_offset(e) + 16) #define ecap_coherent(e) ((e) & 0x1) #define ecap_qis(e) ((e) & 0x2) #define ecap_pass_through(e) ((e >> 6) & 0x1) @@ -180,6 +189,9 @@ static inline void dmar_writeq(void __iomem *addr, u64 val) #define DMA_GSTS_IRES (((u32)1) << 25) #define DMA_GSTS_CFIS (((u32)1) << 23) +/* DMA_RTADDR_REG */ +#define DMA_RTADDR_RTT (((u64)1) << 11) + /* CCMD_REG */ #define DMA_CCMD_ICC (((u64)1) << 63) #define DMA_CCMD_GLOBAL_INVL (((u64)1) << 61) |