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-rw-r--r--arch/arm64/boot/dts/hisilicon/Makefile1
-rw-r--r--arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts35
-rw-r--r--arch/arm64/boot/dts/hisilicon/hi3670.dtsi162
-rw-r--r--arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi181
-rw-r--r--arch/arm64/boot/dts/hisilicon/hi6220.dtsi7
5 files changed, 291 insertions, 95 deletions
diff --git a/arch/arm64/boot/dts/hisilicon/Makefile b/arch/arm64/boot/dts/hisilicon/Makefile
index 03d93f8ef8a95..f4d68caeba831 100644
--- a/arch/arm64/boot/dts/hisilicon/Makefile
+++ b/arch/arm64/boot/dts/hisilicon/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_HISI) += hi3660-hikey960.dtb
+dtb-$(CONFIG_ARCH_HISI) += hi3670-hikey970.dtb
dtb-$(CONFIG_ARCH_HISI) += hi3798cv200-poplar.dtb
dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb
dtb-$(CONFIG_ARCH_HISI) += hip05-d02.dtb
diff --git a/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts b/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts
new file mode 100644
index 0000000000000..4f5118642024c
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Hisilicon HiKey970 Development Board
+ *
+ * Copyright (C) 2016, Hisilicon Ltd.
+ * Copyright (C) 2018, Linaro Ltd.
+ *
+ */
+
+/dts-v1/;
+
+#include "hi3670.dtsi"
+
+/ {
+ model = "HiKey970";
+ compatible = "hisilicon,hi3670-hikey970", "hisilicon,hi3670";
+
+ aliases {
+ serial6 = &uart6; /* console UART */
+ };
+
+ chosen {
+ stdout-path = "serial6:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ /* expect bootloader to fill in this region */
+ reg = <0x0 0x0 0x0 0x0>;
+ };
+};
+
+&uart6 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
new file mode 100644
index 0000000000000..c90e6f6a34ec0
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
@@ -0,0 +1,162 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Hisilicon Hi3670 SoC
+ *
+ * Copyright (C) 2016, Hisilicon Ltd.
+ * Copyright (C) 2018, Linaro Ltd.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "hisilicon,hi3670";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ core2 {
+ cpu = <&cpu2>;
+ };
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+ cluster1 {
+ core0 {
+ cpu = <&cpu4>;
+ };
+ core1 {
+ cpu = <&cpu5>;
+ };
+ core2 {
+ cpu = <&cpu6>;
+ };
+ core3 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ };
+
+ cpu2: cpu@2 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x2>;
+ enable-method = "psci";
+ };
+
+ cpu3: cpu@3 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x3>;
+ enable-method = "psci";
+ };
+
+ cpu4: cpu@100 {
+ compatible = "arm,cortex-a73", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ };
+
+ cpu5: cpu@101 {
+ compatible = "arm,cortex-a73", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x101>;
+ enable-method = "psci";
+ };
+
+ cpu6: cpu@102 {
+ compatible = "arm,cortex-a73", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x102>;
+ enable-method = "psci";
+ };
+
+ cpu7: cpu@103 {
+ compatible = "arm,cortex-a73", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x103>;
+ enable-method = "psci";
+ };
+ };
+
+ gic: interrupt-controller@e82b0000 {
+ compatible = "arm,gic-400";
+ reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */
+ <0x0 0xe82b2000 0 0x2000>, /* GICC */
+ <0x0 0xe82b4000 0 0x2000>, /* GICH */
+ <0x0 0xe82b6000 0 0x2000>; /* GICV */
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ interrupt-controller;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) |
+ IRQ_TYPE_LEVEL_LOW)>;
+ clock-frequency = <1920000>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ uart6_clk: clk_19_2M {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <19200000>;
+ };
+
+ uart6: serial@fff32000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0xfff32000 0x0 0x1000>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&uart6_clk &uart6_clk>;
+ clock-names = "uartclk", "apb_pclk";
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi
index 7afee5d5087b0..68c52f1149be6 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi
@@ -20,22 +20,18 @@
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
clock-names = "apb_pclk";
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
+ out-ports {
+ port {
soc_funnel_out: endpoint {
remote-endpoint =
<&etf_in>;
};
};
+ };
- port@1 {
- reg = <0>;
+ in-ports {
+ port {
soc_funnel_in: endpoint {
- slave-mode;
remote-endpoint =
<&acpu_funnel_out>;
};
@@ -49,21 +45,17 @@
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
clock-names = "apb_pclk";
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
+ in-ports {
+ port {
etf_in: endpoint {
- slave-mode;
remote-endpoint =
<&soc_funnel_out>;
};
};
+ };
- port@1 {
- reg = <0>;
+ out-ports {
+ port {
etf_out: endpoint {
remote-endpoint =
<&replicator_in>;
@@ -77,20 +69,20 @@
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
clock-names = "apb_pclk";
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
+ in-ports {
+ port {
replicator_in: endpoint {
- slave-mode;
remote-endpoint =
<&etf_out>;
};
};
+ };
- port@1 {
+ out-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
reg = <0>;
replicator_out0: endpoint {
remote-endpoint =
@@ -98,7 +90,7 @@
};
};
- port@2 {
+ port@1 {
reg = <1>;
replicator_out1: endpoint {
remote-endpoint =
@@ -114,14 +106,9 @@
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
clock-names = "apb_pclk";
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
+ in-ports {
+ port {
etr_in: endpoint {
- slave-mode;
remote-endpoint =
<&replicator_out0>;
};
@@ -135,14 +122,9 @@
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
clock-names = "apb_pclk";
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
+ in-ports {
+ port {
tpiu_in: endpoint {
- slave-mode;
remote-endpoint =
<&replicator_out1>;
};
@@ -156,85 +138,78 @@
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
clock-names = "apb_pclk";
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
+ out-ports {
+ port {
acpu_funnel_out: endpoint {
remote-endpoint =
<&soc_funnel_in>;
};
};
+ };
- port@1 {
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
reg = <0>;
acpu_funnel_in0: endpoint {
- slave-mode;
remote-endpoint =
<&etm0_out>;
};
};
- port@2 {
+ port@1 {
reg = <1>;
acpu_funnel_in1: endpoint {
- slave-mode;
remote-endpoint =
<&etm1_out>;
};
};
- port@3 {
+ port@2 {
reg = <2>;
acpu_funnel_in2: endpoint {
- slave-mode;
remote-endpoint =
<&etm2_out>;
};
};
- port@4 {
+ port@3 {
reg = <3>;
acpu_funnel_in3: endpoint {
- slave-mode;
remote-endpoint =
<&etm3_out>;
};
};
- port@5 {
+ port@4 {
reg = <4>;
acpu_funnel_in4: endpoint {
- slave-mode;
remote-endpoint =
<&etm4_out>;
};
};
- port@6 {
+ port@5 {
reg = <5>;
acpu_funnel_in5: endpoint {
- slave-mode;
remote-endpoint =
<&etm5_out>;
};
};
- port@7 {
+ port@6 {
reg = <6>;
acpu_funnel_in6: endpoint {
- slave-mode;
remote-endpoint =
<&etm6_out>;
};
};
- port@8 {
+ port@7 {
reg = <7>;
acpu_funnel_in7: endpoint {
- slave-mode;
remote-endpoint =
<&etm7_out>;
};
@@ -251,10 +226,12 @@
cpu = <&cpu0>;
- port {
- etm0_out: endpoint {
- remote-endpoint =
- <&acpu_funnel_in0>;
+ out-ports {
+ port {
+ etm0_out: endpoint {
+ remote-endpoint =
+ <&acpu_funnel_in0>;
+ };
};
};
};
@@ -268,10 +245,12 @@
cpu = <&cpu1>;
- port {
- etm1_out: endpoint {
- remote-endpoint =
- <&acpu_funnel_in1>;
+ out-ports {
+ port {
+ etm1_out: endpoint {
+ remote-endpoint =
+ <&acpu_funnel_in1>;
+ };
};
};
};
@@ -285,10 +264,12 @@
cpu = <&cpu2>;
- port {
- etm2_out: endpoint {
- remote-endpoint =
- <&acpu_funnel_in2>;
+ out-ports {
+ port {
+ etm2_out: endpoint {
+ remote-endpoint =
+ <&acpu_funnel_in2>;
+ };
};
};
};
@@ -302,10 +283,12 @@
cpu = <&cpu3>;
- port {
- etm3_out: endpoint {
- remote-endpoint =
- <&acpu_funnel_in3>;
+ out-ports {
+ port {
+ etm3_out: endpoint {
+ remote-endpoint =
+ <&acpu_funnel_in3>;
+ };
};
};
};
@@ -319,10 +302,12 @@
cpu = <&cpu4>;
- port {
- etm4_out: endpoint {
- remote-endpoint =
- <&acpu_funnel_in4>;
+ out-ports {
+ port {
+ etm4_out: endpoint {
+ remote-endpoint =
+ <&acpu_funnel_in4>;
+ };
};
};
};
@@ -336,10 +321,12 @@
cpu = <&cpu5>;
- port {
- etm5_out: endpoint {
- remote-endpoint =
- <&acpu_funnel_in5>;
+ out-ports {
+ port {
+ etm5_out: endpoint {
+ remote-endpoint =
+ <&acpu_funnel_in5>;
+ };
};
};
};
@@ -353,10 +340,12 @@
cpu = <&cpu6>;
- port {
- etm6_out: endpoint {
- remote-endpoint =
- <&acpu_funnel_in6>;
+ out-ports {
+ port {
+ etm6_out: endpoint {
+ remote-endpoint =
+ <&acpu_funnel_in6>;
+ };
};
};
};
@@ -370,10 +359,12 @@
cpu = <&cpu7>;
- port {
- etm7_out: endpoint {
- remote-endpoint =
- <&acpu_funnel_in7>;
+ out-ports {
+ port {
+ etm7_out: endpoint {
+ remote-endpoint =
+ <&acpu_funnel_in7>;
+ };
};
};
};
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index 247024df714fc..97d5bf2c6ec58 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -99,6 +99,7 @@
reg = <0x0 0x1>;
enable-method = "psci";
next-level-cache = <&CLUSTER0_L2>;
+ clocks = <&stub_clock 0>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
#cooling-cells = <2>; /* min followed by max */
@@ -111,6 +112,7 @@
reg = <0x0 0x2>;
enable-method = "psci";
next-level-cache = <&CLUSTER0_L2>;
+ clocks = <&stub_clock 0>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
#cooling-cells = <2>; /* min followed by max */
@@ -123,6 +125,7 @@
reg = <0x0 0x3>;
enable-method = "psci";
next-level-cache = <&CLUSTER0_L2>;
+ clocks = <&stub_clock 0>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
#cooling-cells = <2>; /* min followed by max */
@@ -135,6 +138,7 @@
reg = <0x0 0x100>;
enable-method = "psci";
next-level-cache = <&CLUSTER1_L2>;
+ clocks = <&stub_clock 0>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
#cooling-cells = <2>; /* min followed by max */
@@ -147,6 +151,7 @@
reg = <0x0 0x101>;
enable-method = "psci";
next-level-cache = <&CLUSTER1_L2>;
+ clocks = <&stub_clock 0>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
#cooling-cells = <2>; /* min followed by max */
@@ -159,6 +164,7 @@
reg = <0x0 0x102>;
enable-method = "psci";
next-level-cache = <&CLUSTER1_L2>;
+ clocks = <&stub_clock 0>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
#cooling-cells = <2>; /* min followed by max */
@@ -171,6 +177,7 @@
reg = <0x0 0x103>;
enable-method = "psci";
next-level-cache = <&CLUSTER1_L2>;
+ clocks = <&stub_clock 0>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
#cooling-cells = <2>; /* min followed by max */
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-30 12:40:08 +0000